- •ADSP-2192M DUAL CORE DSP FEATURES
- •FUNCTIONAL BLOCK DIAGRAM
- •DSP CORE FEATURES
- •TABLE OF CONTENTS
- •GENERAL DESCRIPTION
- •Figure 1. ADSP-219x DSP Core
- •DSP Core Architecture
- •DSP Peripherals
- •Memory Architecture
- •Figure 2. ADSP-2192M Internal/External Memory, Boot Memory, and I/O Memory Maps
- •Interrupts
- •DMA Controller
- •External Interfaces
- •PCI 2.2 Host Interface
- •USB 1.1 Host Interface
- •Sub-ISA Interface
- •CardBus Interface
- •AC’97 2.1 External Codec Interface
- •Serial EEPROM Interface
- •Internal Interfaces
- •Register Interface
- •Register Spaces
- •PCI Configuration Space
- •DSP Core Register Space
- •Peripheral Device Control Register Space
- •USB Register Space
- •CardBus Interface
- •Using the PCI Interface
- •Target/Slave Interface
- •Bus Master Interface
- •PCI Interrupts
- •PCI Control Register.
- •PCI Configuration Space
- •Similarities Between the Three PCI Functions
- •Interactions Between the Three PCI Configurations
- •PCI Memory Map
- •Figure 3. PCI Addressing for 24-Bit and 16-Bit Memory Blocks in 24-Bit Access (BAR2) Mode
- •Figure 4. PCI Addressing for 24-Bit and 16-Bit Memory Blocks in 16-Bit Access (BAR3) Mode
- •24-Bit PCI DSP Memory Map (BAR2)
- •16-Bit PCI DSP Memory Map (BAR3)
- •16-Bit PCI DSP I/O Memory Map (BAR4)
- •Using the USB Interface
- •USB DSP Register Definitions
- •USB DSP Memory Buffer Base Addr Register
- •USB DSP Memory Buffer Size Register
- •USB DSP Memory Buffer RD Pointer Offset Register
- •USB DSP Memory Buffer WR Pointer Offset Register
- •USB Descriptor Vendor ID
- •USB Descriptor Product ID
- •USB Descriptor Release Number
- •USB Descriptor Device Attributes
- •USB DSP MCU Register Definitions
- •USB Endpoint Description Register
- •USB Endpoint NAK Counter Register
- •USB Endpoint Stall Policy Register
- •USB Endpoint 1 Code Download Base Address Register
- •USB Endpoint 2 Code Download Base Address Register
- •USB Endpoint 3 Code Download Base Address Register
- •USB Endpoint 1 Code Current Write Pointer Offset Register
- •USB Endpoint 2 Code Current Write Pointer Offset Register
- •USB Endpoint 3 Code Current Write Pointer Offset Register
- •USB SETUP Token Command Register
- •USB SETUP Token Data Register
- •USB SETUP Counter Register
- •USB Register I/O Address Register
- •USB Register I/O Data Register
- •USB Control Register
- •USB Address/Endpoint Register
- •USB Frame Number Register
- •General USB Device Definitions
- •Configuration 0, 1, and 2 Device Definition
- •Endpoint 0 Definition
- •USB MCU Code Download
- •USB REGIO (Write)
- •USB REGIO (Read)
- •DSP Code Download
- •Example Initialization Process
- •USB Data Pipe Operations
- •OUT Transactions (Host to Device)
- •IN Transactions (Device to Host)
- •Sub-ISA Interface
- •PCI Interface to DSP Memory
- •USB Interface to DSP Memory
- •AC’97 Codec Interface to DSP Memory
- •Data FIFO Architecture
- •FIFO Control Registers
- •System Reset Description
- •Power-On Reset
- •DSP Software Reset
- •Booting Modes
- •Figure 5. Boot Process Flow
- •Power Management Description
- •Power Regulators
- •Low Power Operation
- •Clock Signals
- •Figure 7. External Crystal Connections
- •Figure 8. Clock Domains
- •Instruction Set Description
- •Development Tools
- •Designing an Emulator-Compatible DSP Board (Target)
- •Target Board Header
- •Figure 9. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place)
- •Figure 10. JTAG Target Board Connector with No Local Boundary Scan
- •JTAG Emulator Pod Connector
- •Figure 11. JTAG Pod Connector Dimensions
- •Figure 12. JTAG Pod Connector Keep-Out Area
- •Design-for-Emulation Circuit Information
- •Additional Information
- •PIN DESCRIPTIONS
- •SPECIFICATIONS
- •ABSOLUTE MAXIMUM RATINGS
- •ESD SENSITIVITY
- •TIMING SPECIFICATIONS
- •Programmable Flags Cycle Timing
- •Figure 13. Programmable Flags Cycle Timing
- •Sub-ISA Interface Read/Write Cycle Timing
- •Figure 14. Sub-ISA Interface Read Cycle Timing
- •Figure 15. Sub-ISA Interface Write Cycle Timing
- •Output Drive Currents
- •Figure 16. Typical Drive Currents
- •Power Dissipation
- •Test Conditions
- •Output Disable Time
- •Figure 17. Output Enable/Disable
- •Figure 18. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
- •Figure 19. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
- •Output Enable Time
- •Example System Hold Time Calculation
- •Capacitive Loading
- •Environmental Conditions
- •144-Lead LQFP Pinout
- •OUTLINE DIMENSIONS
- •ORDERING GUIDE
ADSP-2192M
Table 8. 24-Bit PCI DSP Memory Map (BAR2 Mode)1 (continued)
Block |
Byte3 |
Byte2 |
Byte1 |
Byte0 |
Offset |
|
|
|
|
|
|
DSP P0 Program ROM |
UNUSED |
D[23:16] |
D[15:8] |
D[7:0] |
0x0005 0000 |
Block |
UNUSED |
D[23:16] |
D[15:8] |
D[7:0] |
0x0005 0004 |
|
. . . |
. . . |
. . . |
. . . |
. . . |
|
UNUSED |
D[23:16] |
D[15:8] |
D[7:0] |
0x0005 3FFC |
|
|
|
|
|
|
Reserved Space |
RESERVED |
RESERVED |
RESERVED |
RESERVED |
0x0005 4000 |
|
. . . |
. . . |
. . . |
. . . |
. . . |
|
RESERVED |
RESERVED |
RESERVED |
RESERVED |
0x0007 FFFC |
|
|
|
|
|
|
DSP P1 Data RAM |
UNUSED |
D[15:8] |
D[7:0] |
UNUSED |
0x0008 0000 |
Block 0 |
UNUSED |
D[15:8] |
D[7:0] |
UNUSED |
0x0008 0004 |
|
. . . |
. . . |
. . . |
. . . |
. . . |
|
UNUSED |
D[15:8] |
D[7:0] |
UNUSED |
0x0008 FFFC |
|
|
|
|
|
|
DSP P1 Data RAM |
UNUSED |
D[15:8] |
D[7:0] |
UNUSED |
0x0009 0000 |
Block 1 |
UNUSED |
D[15:8] |
D[7:0] |
UNUSED |
0x0009 0004 |
|
. . . |
. . . |
. . . |
. . . |
. . . |
|
UNUSED |
D[15:8] |
D[7:0] |
UNUSED |
0x0009 FFFC |
|
|
|
|
|
|
Reserved Space |
UNUSED |
D[15:8] |
D[7:0] |
UNUSED |
0x000A 0000 |
|
UNUSED |
D[15:8] |
D[7:0] |
UNUSED |
0x000A 0004 |
|
. . . |
. . . |
. . . |
. . . |
. . . |
|
UNUSED |
D[15:8] |
D[7:0] |
UNUSED |
0x000B FFFC |
|
|
|
|
|
|
DSP P1 Program RAM |
UNUSED |
D[23:16] |
D[15:8] |
D[7:0] |
0x000C 0000 |
Block |
UNUSED |
D[23:16] |
D[15:8] |
D[7:0] |
0x000C 0004 |
|
. . . |
. . . |
. . . |
. . . |
. . . |
|
UNUSED |
D[23:16] |
D[15:8] |
D[7:0] |
0x000C FFFC |
|
|
|
|
|
|
DSP P1 Program ROM |
UNUSED |
D[23:16] |
D[15:8] |
D[7:0] |
0x000D 0000 |
Block |
UNUSED |
D[23:16] |
D[15:8] |
D[7:0] |
0x000D 0004 |
|
. . . |
. . . |
. . . |
. . . |
. . . |
|
UNUSED |
D[23:16] |
D[15:8] |
D[7:0] |
0x000D 3FFC |
|
|
|
|
|
|
Reserved Space |
RESERVED |
RESERVED |
RESERVED |
RESERVED |
0x000D 4000 |
|
. . . |
. . . |
. . . |
. . . |
. . . |
|
RESERVED |
RESERVED |
RESERVED |
RESERVED |
0x000F FFFC |
|
|
|
|
|
|
1The “. . .” entries in this table indicate the continuation of the pattern shown in the first rows of each section.
16-Bit PCI DSP Memory Map (BAR3)
The complete PCI address footprint for the ADSP-2192M DSP Memory Spaces in 16-bit (BAR3) Mode is shown in Table 9.
Table 9. 16-Bit PCI DSP Memory Map (BAR3 Mode)1
Block |
Byte3 |
Byte2 |
Byte1 |
Byte0 |
Offset |
|
|
|
|
|
|
|
|
DSP P0 Data RAM |
D[15:8] |
D[7:0] |
D[15:8] |
D[7:0] |
0x0000 |
0000 |
Block 0 |
D[15:8] |
D[7:0] |
D[15:8] |
D[7:0] |
0x0000 |
0004 |
|
. . . |
. . . |
. . . |
. . . |
. . . |
|
|
D[15:8] |
D[7:0] |
D[15:8] |
D[7:0] |
0x0000 |
7FFC |
|
|
|
|
|
|
|
DSP P0 Data RAM |
D[15:8] |
D[7:0] |
D[15:8] |
D[7:0] |
0x0000 |
8000 |
Block 1 |
D[15:8] |
D[7:0] |
D[15:8] |
D[7:0] |
0x0000 |
8004 |
|
. . . |
. . . |
. . . |
. . . |
. . . |
|
|
D[15:8] |
D[7:0] |
D[15:8] |
D[7:0] |
0x0000 FFFC |
|
|
|
|
|
|
|
|
DSP P0 Data RAM |
D[15:8] |
D[7:0] |
D[15:8] |
D[7:0] |
0x0001 |
0000 |
Block 2 |
D[15:8] |
D[7:0] |
D[15:8] |
D[7:0] |
0x0001 |
0004 |
|
. . . |
. . . |
. . . |
. . . |
. . . |
|
|
D[15:8] |
D[7:0] |
D[15:8] |
D[7:0] |
0x0001 |
7FFC |
|
|
|
|
|
|
|
–12– |
REV. 0 |