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				ADSP-2183


Parameter		Min	Max		Unit

IDMA Write, Long Write Cycle
Timing Requirements:
tIKW	IACK Low before Start of Write1	0			ns
tIKSU	IAD15–0 Data Setup before IACK Low2, 3	0.5tCK + 10			ns
tIKH	IAD15–0 Data Hold after IACK Low2, 3	2			ns
Switching Characteristics:
tIKLW	Start of Write to IACK Low4	1.5tCK			ns
tIKHW	Start of Write to IACK High		15		ns

NOTES

1Start of Write = IS Low and IWR Low.

2If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH. 3If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.

4This is the earliest time for IACK Low from Start of Write. For IDMA Write Cycle relationships, please refer to the ADSP-21xx Family User’s Manual, Third Edition.

tIKW

IACK

tIKHW

tIKLW

IWR

tIKSU	tIKH

IAD15–0

DATA

Figure 16. IDMA Write, Long Write Cycle

REV. C

–21–

ADSP-2183

Parameter		Min	Max	Unit

IDMA Read, Long Read Cycle
Timing Requirements:
tIKR	IACK Low before Start of Read1	0		ns
tIRP	Duration of Read	15		ns
Switching Characteristics:
tIKHR	IACK High after Start of Read1		15	ns
tIKDS	IAD15–0 Data Setup before IACK Low	0.5tCK – 7		ns
tIKDH	IAD15–0 Data Hold after End of Read2	0		ns
tIKDD	IAD15–0 Data Disabled after End of Read2		10	ns
tIRDE	IAD15–0 Previous Data Enabled after Start of Read	0		ns
tIRDV	IAD15–0 Previous Data Valid after Start of Read		15	ns
tIRDH1	IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3	2tCK – 5		ns
tIRDH2	IAD15–0 Previous Data Hold after Start of Read (PM2)4	tCK – 5		ns

NOTES

1Start of Read = IS Low and IRD Low. 2End of Read = IS High or IRD High.

3DM read or first half of PM read.

4Second half of PM read.

IACK
	tIKHR
	tIKR
IS
	tIRP
IRD
	tIRDE	tIKDS	tIKDH
IAD15–0	PREVIOUS		READ
IAD15–0	DATA		DATA
	DATA		DATA
	tIRDV		tIKDD
	tIRDH

Figure 17. IDMA Read, Long Read Cycle

–22–

REV. C

				ADSP-2183


Parameter		Min	Max		Unit

IDMA Read, Short Read Cycle
Timing Requirements:
tIKR	IACK Low before Start of Read1	0			ns
tIRP	Duration of Read	15			ns
Switching Characteristics:
tIKHR	IACK High after Start of Read1		15		ns
tIKDH	IAD15–0 Data Hold after End of Read2	0			ns
tIKDD	IAD15–0 Data Disabled after End of Read2		10		ns
tIRDE	IAD15–0 Previous Data Enabled after Start of Read	0			ns
tIRDV	IAD15–0 Previous Data Valid after Start of Read		15		ns

NOTES

1Start of Read = IS Low and IRD Low. 2End of Read = IS High or IRD High.

	IACK
	tIKR
	tIKHR
	IS
	IRD	tIRP
	tIRDE	tIKDH
	IAD15–0	PREVIOUS
	IAD15–0	DATA
		DATA
	tIRDV	tIKDD

Figure 18. IDMA Read, Short Read Cycle

REV. C

–23–

ADSP-2183

OUTPUT DRIVE CURRENTS

Figure 19 shows typical I-V characteristics for the output drivers of the ADSP-2183. The curves represent the current drive capability of the output drivers as a function of output voltage.

PINT = internal power dissipation from Power vs. Frequency graph (Figure 20).

(C × VDD2 × f ) is calculated for each output:

100

# of

Pins

× C

× f

× VDD

Address, DMS

× 10 pF

× 3.32 V

× 33.3 MHz

29.0 mW

– mA

3.6V, –40°C

Data Output, WR 9

× 10 pF

× 3.32 V

× 16.67 MHz =

16.3 mW

3.3V, +25°C

× 10 pF

× 3.32 V

× 16.67 MHz =

1.8 mW

CURRENT

–25

3.0V, +85°C

CLKOUT

× 10 pF

× 3.32 V

× 33.3 MHz

3.6 mW

50.7 mW

–50

3.0V, +85°C

–75

SOURCE

Total power dissipation for this example is PINT + 50.7 mW.

–100

3.3V, +25°C

3.6V, –40°C

2183 POWER, INTERNAL1, 3, 4

–125

220

–150

205

–175

190

184mW

–200

0.75

1.50

2.25

3.00

3.75

4.50

175

5.25

SOURCE VOLTAGE – V

160

VDD = 3.6V

150mW

Figure 19. Typical Drive Currents

145

1000

130

VDD = 3.3V

110mW

120mW

115

VDD = 3.0V

100 90mW

– A

VDD = 3.6V

85 72mW

VDD = 3.3V

SCALE)

100

VDD = 3.0V

1/tCK – MHz

POWER, IDLE1, 2, 3

(LOG

CURRENT

38mW

VDD = 3.6V

30mW

30 27mW

VDD = 3.3V

20mW

24mW

TEMPERATURE – °C

VDD = 3.0V

NOTES:

15mW

1. REFLECTS ADSP-2183 OPERATION IN LOWEST POWER MODE.

(SEE "SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY

USER'S MANUAL FOR DETAILS.)

2. CURRENT REFLECTS DEVICE OPERATING WITH NO INPUT LOADS.

Figure 20. Power-Down Supply Current (Typical)

1/tCK – MHz

POWER DISSIPATION

POWER, IDLE n MODES3

30mW

To determine total power dissipation in a specific application,

IDLE

the following equation should be applied for each output:

C × VDD2 × f

C = load capacitance, f = output switching frequency.

Example:

20mW

In an application where external data memory is used and no

13.8mW

other outputs are active, power dissipation is calculated as

IDLE (16)

follows:

12 11mW

IDLE (128)

13mW

Assumptions:

10.6mW

• External data memory is accessed every cycle with 50% of the

1/tCK – MHz

address pins switching.

VALID FOR ALL TEMPERATURE GRADES.

• External data memory writes occur every other cycle with

1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2IDLE REFERS TO ADSP-2183 STATE OF OPERATION DURING EXECUTION OF IDLE

50% of the data pins switching.

INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.

3TYPICAL POWER DISSIPATION AT 3.3V V

AND 25 C EXCEPT WHERE SPECIFIED.

• Each address and data pin has a 10 pF total load at the pin.

4IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL

MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1,4,5,12,13,14),

• The application operates at VDD = 3.3 V and tCK = 30.0 ns.

30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.

Total Power Dissipation = PINT

+ (C × VDD2 × f )

Figure 21. Power vs. Frequency

–24–

REV. C

CAPACITIVE LOADING

Figures 22 and 23 show the capacitive loading characteristics of the ADSP-2183.

	25
	25
		T =	+85 C
		VDD = 3.0V
2.4V) – ns	20
	20
	15
	15
(0.4V –	10
RISE TIME

	5
	5
	0
	0	20		40	60	80	100	120	140	160	180	200
	0	20		40	60	80	100	120	140	160	180	200

CL – pF

Figure 22. Typical Output Rise Time vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature)

		18
		16
DELAY	ns	14
DELAY	ns	12
		12
OUTPUTVALID	HOLDOR–	10
OUTPUTVALID	HOLDOR–	8
		8
		6
		4
		2

NOMINAL

–2

–4

–6

0	40	80	120	160	200
			CL – pF

Figure 23. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature)

TEST CONDITIONS

Output Disable Time

Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The out-

put disable time (tDIS) is the difference of tMEASURED and tDECAY, as shown in the Output Enable/Disable diagram. The time is the

interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. The decay time,

tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the fol-

lowing equation:

tDECAY = CL •i0.5V

from which

tDIS = tMEASURED – tDECAY

ADSP-2183

is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving.

INPUT	1.5V	1.5V
OR

OUTPUT

Figure 24. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)

Output Enable Time

Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.

REFERENCE

SIGNAL

tMEASURED

tENA

VOH

tDIS

VOH

(MEASURED)

VOH (MEASURED) – 0.5V

2.0V

(MEASURED)

OUTPUT

VOL (MEASURED) +0.5V

1.0V

VOL

tDECAY

VOL

(MEASURED)

OUTPUT STARTS

OUTPUT STOPS

DRIVING

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

Figure 25. Output Enable/Disable

IOL

OUTPUT +1.5V

50pF

IOH

Figure 26. Equivalent Device Loading for AC Measurements (Including All Fixtures)

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

TAMB = TCASE – (PD × θCA)

TCASE = Case Temperature in °C PD = Power Dissipation in W

θCA = Thermal Resistance (Case-to-Ambient)

θJA = Thermal Resistance (Junction-to-Ambient)

θJC = Thermal Resistance (Junction-to-Case)

Package	JA	JC	CA
LQFP	50°C/W	2°C/W	48°C/W
Mini-BGA	70.7°C/W	7.4°C/W	63.3°C/W

REV. C

–25–

ADSP-2183

128-Lead LQFP Package Pinout

IAL 1

PF3 2

PF2 3

PF1 4

PF0 5

WR 6

RD 7

IOMS 8

BMS 9

DMS 10

CMS 11

GND 12

VDD 13

PMS 14

A0 15

A1 16

A2 17

A3 18

A4 19

A5 20

A6 21

A7 22

XTAL 23

CLKIN 24

GND 25

CLKOUT 26

GND 27

VDD 28

A8 29

A9 30

A10 31

A11 32

A12 33

A13 34

IRQE 35

MMAP 36

PWD 37

IRQ2 38

IS	GND	PF4	PF5	PF6	PF7	IAD0	IAD1	IAD2	IAD3	IAD4	IAD5	GND	V	IAD6	IAD7	IAD8	IAD9	IAD10	IAD11	IAD12	IAD13	IAD14	IAD15	IRD	IWR
													DD
128	127	126	125	124	123	122	121	120	119	118	117	116	115	114	113	112	111	110	109	108	107	106	105	104	103

PIN 1

IDENTIFIER

ADSP-2183

TOP VIEW (Not to Scale)

39	40	41	42	43	44	45	46	47	48	49	50	51	52	53	54	55	56	57	58	59	60	61	62	63	64

BMODE	PWDACK	IACK	BGH	V	GND	IRQL0	IRQL1	FL0	FL1	FL2	DT0	TFS0	RFS0	DR0	SCLK0	DT1/F0	TFS1/IRQ1	RFS1/IRQ0	GND	DR1/FI	SCLK1	ERESET	RESET	EMS	EE
				DD

102	GND

101	D23

100	D22

99	D21

98	D20
	D19
97	D19

96	D18

95	D17

94	D16

93	D15
	GND
92	GND

91	VDD

90	GND

89	D14

88	D13
	D12
87	D12

86	D11

85	D10

84	D9

83	D8
	D7
82	D7

81	D6

80	D5
	GND
79	GND

78	D4
	D3
77	D3

76	D2

75	D1
	D0
74	D0

73	VDD

72	BG

71	EBG

70	BR

69	EBR

68	EINT
	ELIN
67	ELIN
	ELOUT
66	ELOUT
	ECLK
65	ECLK

–26–

REV. C

ADSP-2183

LQFP Pin Configurations

LQFP	Pin	LQFP	Pin	LQFP	Pin	LQFP	Pin
Number	Name	Number	Name	Number	Name	Number	Name

1	IAL	33	A12	65	ECLK	97	D19
2	PF3	34	A13	66	ELOUT	98	D20
3	PF2	35	IRQE	67	ELIN	99	D21
4	PF1	36	MMAP	68	EINT	100	D22
5	PF0	37	PWD	69	EBR	101	D23
6	WR	38	IRQ2	70	BR	102	GND
7	RD	39	BMODE	71	EBG	103	IWR
8	IOMS	40	PWDACK	72	BG	104	IRD
9	BMS	41	IACK	73	VDD	105	IAD15
10	DMS	42	BGH	74	D0	106	IAD14
11	CMS	43	VDD	75	D1	107	IAD13
12	GND	44	GND	76	D2	108	IAD12
13	VDD	45	IRQL0	77	D3	109	IAD11
14	PMS	46	IRQL1	78	D4	110	IAD10
15	A0	47	FL0	79	GND	111	IAD9
16	A1	48	FL1	80	D5	112	IAD8
17	A2	49	FL2	81	D6	113	IAD7
18	A3	50	DT0	82	D7	114	IAD6
19	A4	51	TFS0	83	D8	115	VDD
20	A5	52	RFS0	84	D9	116	GND
21	A6	53	DR0	85	D10	117	IAD5
22	A7	54	SCLK0	86	D11	118	IAD4
23	XTAL	55	DT1/F0	87	D12	119	IAD3
24	CLKIN	56	TFS1/IRQ1	88	D13	120	IAD2
25	GND	57	RFS1/IRQ0	89	D14	121	IAD1
26	CLKOUT	58	GND	90	GND	122	IAD0
27	GND	59	DR1/FI	91	VDD	123	PF7
28	VDD	60	SCLK1	92	GND	124	PF6
29	A8	61	ERESET	93	D15	125	PF5
30	A9	62	RESET	94	D16	126	PF4
31	A10	63	EMS	95	D17	127	GND
32	A11	64	EE	96	D18	128	IS

REV. C

–27–

ADSP-2183

144-Lead Mini-BGA Package Pinout

(Bottom View)

GND

IWR

IAD14

IAD10

IAD6

GND

IAD2

PF6

GND

IAL

D21

D23

IRD

IAD15

IAD11

VDD

GND

IAD1

PF5

GND

PF3

PF1

D17

D20

D22

IAD13

IAD8

VDD

IAD0

PF4

PF2

PF0

GND

D15

D18

D19

D16

IAD9

IAD5

PF7

IOMS

GND

DMS

GND

D14

GND

VDD

GND

IAD7

CMS

IAD3

BMS

VDD

D10

D11

D13

D12

IAD12

IAD4

PMS

DT0

GND

XTAL

GND

DT1

IRQL0

VDD

GND

CLKIN

VDD

RFS1

SCLK0

IRQL1

VDD

A10

VDD

CLKOUT

EBG

EBR

ERESET

SCLK1

TFS1

TFS0

FL2

PWDACK

A11

A12

EINT

ELOUT

ELIN

RESET

GND

DR0

FL0

GND

IACK

IRQE

MMAP

A13

ECLK

EMS

DR1

GND

RFS0

FL1

GND

BGH

BMODE

IRQ2

PWD

–28–

REV. C

ADSP-2183

Mini-BGA Pin Configurations

Ball #	Name	Ball #	Name	Ball #	Name	Ball #	Name

A01	IAL	D01	GND	G01	XTAL	K01	A9
A02	IS	D02	DMS	G02	A5	K02	A12
A03	GND	D03	GND	G03	GND	K03	A11
A04	PF6	D04	IOMS	G04	A6	K04	PWDACK
A05	IAD2	D05	PF7	G05	A8	K05	FL2
A06	GND	D06	IAD5	G06	A7	K06	TFS0
A07	IAD6	D07	IAD9	G07	DT0	K07	TFS1
A08	IAD10	D08	D16	G08	D7	K08	SCLK1
A09	IAD14	D09	D19	G09	D4	K09	ERESET
A10	IWR	D10	D18	G10	D9	K10	EBR
A11	GND	D11	D15	G11	D5	K11	BR
A12	GND	D12	GND	G12	D6	K12	EBG
B01	PF1	E01	VDD	H01	CLKIN	L01	A13
B02	PF3	E02	VDD	H02	GND	L02	MMAP
B03	GND	E03	A0	H03	GND	L03	IRQE
B04	PF5	E04	BMS	H04	GND	L04	IACK
B05	IAD1	E05	IAD3	H05	VDD	L05	GND
B06	GND	E06	CMS	H06	IRQL0	L06	FL0
B07	VDD	E07	IAD7	H07	DT1	L07	DR0
B08	IAD11	E08	GND	H08	D3	L08	GND
B09	IAD15	E09	GND	H09	D0	L09	RESET
B10	IRD	E10	VDD	H10	GND	L10	ELIN
B11	D23	E11	GND	H11	D2	L11	ELOUT
B12	D21	E12	D14	H12	GND	L12	EINT
C01	RD	F01	A2	J01	CLKOUT	M01	PWD
C02	PF0	F02	A1	J02	VDD	M02	IRQ2
C03	WR	F03	A4	J03	A10	M03	BMODE
C04	PF2	F04	A3	J04	VDD	M04	BGH
C05	PF4	F05	PMS	J05	VDD	M05	GND
C06	IAD0	F06	IAD4	J06	IRQL1	M06	FL1
C07	VDD	F07	D8	J07	SCLK0	M07	RFS0
C08	IAD8	F08	IAD12	J08	RFS1	M08	GND
C09	IAD13	F09	D12	J09	BG	M09	DR1
C10	D22	F10	D13	J10	D1	M10	EMS
C11	D20	F11	D11	J11	VDD	M11	EE
C12	D17	F12	D10	J12	VDD	M12	ECLK

REV. C

–29–

ADSP-2183

OUTLINE DIMENSIONS

Dimensions given in mm and (inches).

128-Lead Metric Plastic Thin Quad Flatpack (LQFP)

(ST-128)

		16.20 (0.638)
		16.00 (0.630)
1.60 (0.063)		15.80 (0.622)
MAX
0.75 (0.030)
0.60 (0.024)	128	103
0.50 (0.020)	128	103
0.50 (0.020)	1	102
SEATING
PLANE

					TOP VIEW						22.20 (0.874)		22.00 (0.866)	21.80 (0.858)





					(PINS DOWN)				20.10 (0.792)	20.00 (0.787)		19.90 (0.783)
















0.08 (0.003)

		38						65
MAX LEAD		39						64
COPLANARITY		39						64
COPLANARITY
0.15 (0.006)
0.15 (0.006)		0.50 (0.020)					0.27 (0.011)

0.05 (0.002)

				BSC			0.22 (0.009)
				BSC			0.22 (0.009)
1.45 (0.057)			LEAD PITCH				0.17 (0.007)
						LEAD WIDTH
	1.40 (0.055)					LEAD WIDTH
	1.40 (0.055)

	1.35 (0.053)	14.10 (0.555)

					14.00 (0.551)
					14.00 (0.551)
					13.90 (0.547)

NOTES:

THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 (0.0032) FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION.

CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED

–30–

REV. C

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