- •ADSP-2196
- •ADSP-219x dSP Core Features
- •ADSP-2196 DSP Features
- •TABLE OF CONTENTS
- •General Note
- •General Description
- •DSP Core Architecture
- •DSP Peripherals Architecture
- •Memory Architecture
- •Internal (On-Chip) Memory
- •Internal On-Chip ROM
- •On-Chip Memory Security
- •External (Off-Chip) Memory
- •External Memory Space
- •I/O Memory Space
- •Boot Memory Space
- •Interrupts
- •DMA Controller
- •Host Port
- •Host Port Acknowledge (HACK) Modes
- •Host Port Chip Selects
- •DSP Serial Ports (SPORTs)
- •Serial Peripheral Interface (SPI) Ports
- •UART Port
- •Programmable Flag (PFx) Pins
- •Low Power Operation
- •Idle Mode
- •Power-down Core Mode
- •Power-Down Core/Peripherals Mode
- •Power-Down All Mode
- •Clock Signals
- •Reset
- •Power Supplies
- •Booting Modes
- •Bus Request and Bus Grant
- •Instruction Set Description
- •Development Tools
- •Designing an Emulator-Compatible DSP Board (Target)
- •Target Board Header
- •JTAG Emulator Pod Connector
- •Design-for-Emulation Circuit Information
- •Additional Information
- •Pin Descriptions
- •Specifications
- •ABSOLUTE MAXIMUM RATINGS
- •ESD SENSITIVITY
- •Timing Specifications
- •Clock In and Clock Out Cycle Timing
- •Programmable Flags Cycle Timing
- •Timer PWM_OUT Cycle Timing
- •External Port Write Cycle Timing
- •External Port Read Cycle Timing
- •External Port Bus Request and Grant Cycle Timing
- •Host Port ALE Mode Write Cycle Timing
- •Host Port ACC Mode Write Cycle Timing
- •Host Port ALE Mode Read Cycle Timing
- •Host Port ACC Mode Read Cycle Timing
- •Serial Port (SPORT) Clocks and Data Timing
- •Serial Port (SPORT) Frame Synch Timing
- •Serial Peripheral Interface (SPI) Port—Master Timing
- •Serial Peripheral Interface (SPI) Port—Slave Timing
- •Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing
- •JTAG Test And Emulation Port Timing
- •Output Drive Currents
- •Power Dissipation
- •Test Conditions
- •Output Disable Time
- •Output Enable Time
- •Capacitive Loading
- •Environmental Conditions
- •Thermal Characteristics
- •ADSP-2196 144-Lead LQFP Pinout
- •ADSP-2196 144-Lead Mini-BGA Pinout
- •Outline Dimensions
- •Ordering Guide
35(/,0,1$5< 7(&+1,&$/ '$7$
a |
DSP Microcomputer |
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Preliminary Technical Data |
ADSP-2196 |
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ADSP-219x DSP CORE FEATURES |
Independent ALU, Multiplier/Accumulator, and Barrel |
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6.25 ns Instruction Cycle Time (Internal), for up to |
Shifter Computational Units with Dual 40-bit |
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160 MIPS Sustained Performance |
Accumulators |
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ADSP-218x Family Code Compatible with the Same |
Single-Cycle Context Switch between Two Sets of |
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Easy -to-Use Algebraic Syntax |
Computational and DAG Registers |
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Single-Cycle Instruction Execution |
Parallel Execution of Computation and Memory |
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Up to 16M words of Addressable Memory Space with |
Instructions |
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24 Bits of Addressing Width |
Pipelined Architecture Supports Efficient Code |
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Dual Purpose Program Memory for Both Instruction and |
Execution at Speeds up to 160 MIPS |
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Data Storage |
Register File Computations with All Nonconditional, |
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Fully Transparent Instruction Cache Allows Dual |
Nonparallel Computational Instructions |
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Operand Fetches in Every Instruction Cycle |
Powerful Program Sequencer Provides Zero-Overhead |
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Unified Memory Space Permits Flexible Address |
Looping and Conditional Instruction Execution |
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Generation, Using Two Independent DAG Units |
Architectural Enhancements for Compiled C |
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Code Efficiency |
FUNCTIONAL BLOCK DIAGRAM
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0 ( 0 2 5 < 0 |
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REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 |
World Wide Web Site: http://www.analog.com |
Fax:781/326-8703 |
©Analog Devices,Inc., 2001 |