625-Ball PBGA (B-625)

27.20
27.00		24		22		20		18		16		14		12		10	8	6	4		2
26.80		25	23		21		19		17		15		13		11		9	7	5	3	1
		25	23		21		19		17		15		13		11		9	7	5	3	1
																					A
																					B
		1.50																			C
		1.50																			D
		BSC																			D
		BSC																			E
		SQ																			F
		SQ																			G
																					H
		24.00																			J
		24.00																			K
24.20	27.20	BSC																			L
24.20	27.20	SQ																			M
24.00	27.00	SQ																			N
24.00	27.00																				N
23.80	26.80																				P
23.80	26.80																				R
																					T
		1.00																			U
		BSC																			V
		BSC																			W
		SQ																			Y
		SQ																			AA
		BALL																			AB
		PITCH																			AC
		PITCH																			AD
		1.50																			AE
24.20		1.50										27.20
24.20		BSC										27.20
24.00		BSC										27.00 SQ
		SQ										27.00 SQ
												26.80
23.80												26.80
23.80
TOP VIEW										BOTTOM VIEW
	DETAIL A
2.50 MAX		0.65																	1.25 MAX
		0.65
		0.55
		0.55
		0.45
NOTES:		SEATING PLANE																		0.40 MIN
1. ALL DIMENSIONS ARE IN MILLIMETERS.		SEATING PLANE														0.70
1. ALL DIMENSIONS ARE IN MILLIMETERS.																0.70
2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25mm OF ITS		BALL DIAMETER														0.60				0.20 MAX
IDEAL POSITION RELATIVE TO THE PACKAGE EDGES.																0.50
3. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10mm OF ITS
IDEAL POSITION RELATIVE TO THE BALL GRID.
4. CENTER DIMENSIONS ARE NOMINAL.											DETAIL A

5.THIS PACKAGE COMPLIES WITH THE JEDEC MS-034 SPECIFICATION, BUT USES TIGHTER TOLERANCES THAN THE MAXIMUMS ALLOWED IN THAT SPECIFICATION.

ORDERING GUIDE

	Temperature	Core Clock	On-chip	Operating
Part Number1, 2, 3, 4	Range (Case)	(CCLK) Rate5	SRAM	Voltage	Package

ADSP-TS101SAB1-000	–40°C to +85°C	250 MHz	6M Bit	1.2 VDD	(B-625)6
				3.3 VDD_IO	(B-484)7
ADSP-TS101SAB2-000	–40°C to +85°C	250 MHz	6M Bit	1.2 VDD	(B-484)7
				3.3 VDD_IO
1S indicates 1.2 and 3.3 V supplies.
2A indicates –40°C to +85°C temperature.
3B = Plastic Ball Grid Array (PBGA) package.
41-000 indicates B-625 package and 250 MHz speed grade, and 2-000 indicates B-484 package and 250 MHz speed grade.
5The instruction rate runs at the internal DSP clock (CCLK) rate.
6The B-625 package measures 27 mm × 27 mm.
7The B-484 package measures 19 mm × 19 mm.

C03164–0–9/02(0)

PRINTED IN U.S.A.

–40–

REV. 0

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