- •ADSP-TS101S
- •KEY FEATURES
- •KEY BENEFITS
- •FUNCTIONAL BLOCK DIAGRAM
- •TABLE OF CONTENTS
- •GENERAL DESCRIPTION
- •Figure 1. Single Processor System with External SDRAM
- •Dual Compute Blocks
- •Data Alignment Buffer (DAB)
- •Dual Integer ALUs (IALUs)
- •Program Sequencer
- •Interrupt Controller
- •Flexible Instruction Set
- •On-Chip SRAM Memory
- •Figure 2. Memory Map
- •External Port (Off-Chip Memory/Peripherals Interface)
- •Host Interface
- •Multiprocessor Interface
- •Figure 3. Shared Memory Multiprocessing System
- •SDRAM Controller
- •EPROM Interface
- •DMA Controller
- •Link Ports
- •Timer and General-Purpose I/O
- •Reset and Booting
- •Figure 4. Power-up Reset Waveform
- •Low Power Operation
- •Clock Domains
- •Power Supplies
- •Filtering Reference Voltage and Clocks
- •Figure 5. VREF, SCLK_N, and LCLK_N Filter
- •Development Tools
- •Target Board Header
- •Figure 6. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place)
- •Figure 7. JTAG Target Board Connector with No Local Boundary Scan
- •JTAG Emulator Pod Connector
- •Figure 8. JTAG Pod Connector Dimensions
- •Figure 9. JTAG Pod Connector Keep-Out Area
- •Design for Emulation Circuit Information
- •Additional Information
- •PIN FUNCTION DESCRIPTIONS
- •STRAP PIN FUNCTION DESCRIPTIONS
- •SPECIFICATIONS
- •RECOMMENDED OPERATING CONDITIONS
- •ELECTRICAL CHARACTERISTICS
- •ABSOLUTE MAXIMUM RATINGS
- •ESD SENSITIVITY
- •TIMING SPECIFICATIONS
- •General AC Timing
- •Figure 10. General AC Parameters Timing
- •Link Ports Data Transfer and Token Switch Timing
- •Figure 11. Link Ports—Transmit
- •Figure 12. Link Ports—Receive
- •Figure 13. Link Ports—Token Switch, Token Master
- •Figure 14. Link Ports—Token Switch, Token Requester
- •Output Drive Currents
- •Power Dissipation
- •Test Conditions
- •Figure 24. Output Enable/Disable
- •Output Disable Time
- •Output Enable Time
- •Capacitive Loading
- •Figure 25. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
- •Environmental Conditions
- •Thermal Characteristics
- •OUTLINE DIMENSIONS
- •484-Ball PBGA (B-484)
- •625-Ball PBGA (B-625)
- •ORDERING GUIDE
- •484-BALL PBGA PIN CONFIGURATIONS
- •484-Ball PBGA Pin Configurations (Top View, Summary)
- •625-BALL PBGA PIN CONFIGURATIONS
- •625-Ball PBGA Pin Configurations (Top View, Summary)
ADSP-TS101S
OUTLINE DIMENSIONS
The ADSP-TS101S is available in a 19 mm 19 mm, 484-ball PBGA package with 22 rows of balls (B-484); the DSP also is available in a 27 mm 27 mm, 625-ball PBGA package with 25 rows of balls (B-625).
484-Ball PBGA (B-484)
19.10 |
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22 |
20 |
18 |
16 |
14 |
12 |
10 |
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8 |
6 |
4 |
2 |
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19.00 |
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21 |
19 |
17 |
15 |
13 |
11 |
9 |
7 |
5 |
3 |
1 |
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18.90 |
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A |
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B |
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1.10 |
C |
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BSC |
D |
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E |
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F |
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G |
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H |
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J |
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17.05 |
19.10 |
16.80 |
K |
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BSC |
L |
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19.00 |
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16.95 |
SQ |
M |
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18.90 |
N |
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16.85 |
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P |
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R |
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0.80 |
T |
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BSC |
U |
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SQ |
V |
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W |
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BALL |
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Y |
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PITCH |
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AA |
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1.10 |
AB |
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17.05 |
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19.10 |
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BSC |
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16.95 |
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19.00 SQ |
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16.85 |
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18.90 |
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TOP VIEW
DETAIL A
2.50 MAX
NOTES:
1.ALL DIMENSIONS ARE IN MILLIMETERS.
2.THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25mm OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES.
3.THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10mm OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.
4.CENTER DIMENSIONS ARE NOMINAL.
BOTTOM VIEW
0.65 |
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1.30 MAX |
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0.55 |
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0.45 |
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SEATING PLANE |
0.55 |
0.40 MIN |
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BALL DIAMETER |
0.50 |
0.20 MAX |
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0.45 |
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DETAIL A
REV. 0 |
–39– |
