- •ADSP-TS101S
- •KEY FEATURES
- •KEY BENEFITS
- •FUNCTIONAL BLOCK DIAGRAM
- •TABLE OF CONTENTS
- •GENERAL DESCRIPTION
- •Figure 1. Single Processor System with External SDRAM
- •Dual Compute Blocks
- •Data Alignment Buffer (DAB)
- •Dual Integer ALUs (IALUs)
- •Program Sequencer
- •Interrupt Controller
- •Flexible Instruction Set
- •On-Chip SRAM Memory
- •Figure 2. Memory Map
- •External Port (Off-Chip Memory/Peripherals Interface)
- •Host Interface
- •Multiprocessor Interface
- •Figure 3. Shared Memory Multiprocessing System
- •SDRAM Controller
- •EPROM Interface
- •DMA Controller
- •Link Ports
- •Timer and General-Purpose I/O
- •Reset and Booting
- •Figure 4. Power-up Reset Waveform
- •Low Power Operation
- •Clock Domains
- •Power Supplies
- •Filtering Reference Voltage and Clocks
- •Figure 5. VREF, SCLK_N, and LCLK_N Filter
- •Development Tools
- •Target Board Header
- •Figure 6. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place)
- •Figure 7. JTAG Target Board Connector with No Local Boundary Scan
- •JTAG Emulator Pod Connector
- •Figure 8. JTAG Pod Connector Dimensions
- •Figure 9. JTAG Pod Connector Keep-Out Area
- •Design for Emulation Circuit Information
- •Additional Information
- •PIN FUNCTION DESCRIPTIONS
- •STRAP PIN FUNCTION DESCRIPTIONS
- •SPECIFICATIONS
- •RECOMMENDED OPERATING CONDITIONS
- •ELECTRICAL CHARACTERISTICS
- •ABSOLUTE MAXIMUM RATINGS
- •ESD SENSITIVITY
- •TIMING SPECIFICATIONS
- •General AC Timing
- •Figure 10. General AC Parameters Timing
- •Link Ports Data Transfer and Token Switch Timing
- •Figure 11. Link Ports—Transmit
- •Figure 12. Link Ports—Receive
- •Figure 13. Link Ports—Token Switch, Token Master
- •Figure 14. Link Ports—Token Switch, Token Requester
- •Output Drive Currents
- •Power Dissipation
- •Test Conditions
- •Figure 24. Output Enable/Disable
- •Output Disable Time
- •Output Enable Time
- •Capacitive Loading
- •Figure 25. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
- •Environmental Conditions
- •Thermal Characteristics
- •OUTLINE DIMENSIONS
- •484-Ball PBGA (B-484)
- •625-Ball PBGA (B-625)
- •ORDERING GUIDE
- •484-BALL PBGA PIN CONFIGURATIONS
- •484-Ball PBGA Pin Configurations (Top View, Summary)
- •625-BALL PBGA PIN CONFIGURATIONS
- •625-Ball PBGA Pin Configurations (Top View, Summary)
ADSP-TS101S
Environmental Conditions
The ADSP-TS101S is rated for performance over the extended commercial temperature range, TCASE = –40°C to +85°C.
Thermal Characteristics
The ADSP-TS101S is packaged in a 19 mm × 19 mm and
27 mm × 27 mm Plastic Ball Grid Array (PBGA). The ADSPTS101S is specified for a case temperature (TCASE). To ensure
that the TCASE data sheet specification is not exceeded, a heat sink and/or an air flow source may be used. See Table 24 and
Table 25 for thermal data.
Table 24. Thermal Characteristics for 19 mm × 19 mm Package
Parameter |
Condition |
Typical |
Unit |
|
|
|
|
θJA1 |
Airflow2 = 0 m/s |
16.6 |
°C/W |
|
Airflow3 = 1 m/s |
14.0 |
°C/W |
|
Airflow3 = 2 m/s |
12.9 |
°C/W |
θJC |
– |
6.7 |
°C/W |
θJB |
– |
5.8 |
°C/W |
|
|
|
|
1The determination of θJA is system dependent and is based on a number of factors including device power dissipation, package thermal resistance, board thermal characteristics, ambient temperature, and air flow.
2Per JEDEC JESD51-2 procedure using a four layer board (compliant with JEDEC JESD51-9).
3Per SEMI Test Method G38-87 using a four layer board (compliant with JEDEC JESD51-9).
Table 25. Thermal Characteristics for 27 mm × 27 mm Package
Parameter |
Condition |
Typical |
Unit |
|
|
|
|
θJA1 |
Airflow2 = 0 m/s |
13.8 |
°C/W |
|
Airflow3 = 1 m/s |
11.7 |
°C/W |
|
Airflow3 = 2 m/s |
10.8 |
°C/W |
θJC |
– |
3.1 |
°C/W |
|
|
|
|
θJB |
– |
5.9 |
°C/W |
|
|
|
|
1The determination of θJA is system dependent and is based on a number of factors including device power dissipation, package thermal resistance, board thermal characteristics, ambient temperature, and air flow.
2Per JEDEC JESD51-2 procedure using a four layer board (compliant with JEDEC JESD51-9).
3Per SEMI Test Method G38-87 using a four layer board (compliant with JEDEC JESD51-9).
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