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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / ADSP-TS101S_0.pdf

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ADSP-TS101S

The output enable time tENA is the difference between

tMEASURED_ENA and tRAMP as shown in Figure 24. The time tMEASURED_ENA is the interval from when the reference signal switches to when the output voltage ramps ∆V from the measured

three-stated output level. The tRAMP value is calculated with test load CL, drive current ID, and with ∆V equal to 0.5 V.

Capacitive Loading

Output valid and hold are based on standard capacitive loads: 30 pF on all pins (see Figure 25). The delay and hold specifications given should be derated by a drive strength related factor for loads other than the nominal value of 30 pF. Figure 26 through Figure 33 show how output rise time varies with capacitance. Figure 34 graphically shows how output valid varies with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on Page 29.) The graphs of Figure 26 through Figure 34 may not be linear outside the ranges shown.

TO	50
OUTPUT	1.5V
PIN	30pF
	30pF

Figure 25. Equivalent Device Loading for AC Measurements (Includes All Fixtures)

	25					STRENGTH 0
	25					(VDD_IO = 3.3V)
						(VDD_IO = 3.3V)
–ns	20
TIMES	15		RISE TIME
FALL			RISE TIME
		y = 0.2015x + 3.8869
		y = 0.2015x + 3.8869							FALL TIME

AND	10								y = 0.174x + 2.6931
AND	10
RISE
	5
	0
	0	10	20	30	40	50	60	70	80	90	100
					LOAD CAPACITANCE – pF

Figure 26. Typical Output Rise and Fall Time (10%–90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 0

	25					STRENGTH 1
	25				(VDD_IO = 3.3V)
					(VDD_IO = 3.3V)
–ns	20
ES
TIM	15
LL	15
LL
FA
D			RISE TIME
EAN	10		RISE TIME
	10	y = 0.1349x + 1.9955
		y = 0.1349x + 1.9955						FALL TIME
RIS								FALL TIME
RIS								y = 0.1163x + 1.4058
	5							y = 0.1163x + 1.4058
	5
	0
	0	10	20	30	40	50	60	70	80	90	100
					LOAD CAPACITANCE – pF

Figure 27. Typical Output Rise and Fall Time (10%–90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 1

	25					STRENGTH 2
	25					(VDD_IO = 3.3V)
						(VDD_IO = 3.3V)
–ns	20
ES
TIM	15
LL	15
LL
FA
D			RISE TIME
AN	10		RISE TIME
AN	10	y = 0.1304x + 0.8427
SE		y = 0.1304x + 0.8427							FALL TIME
RI								y = 0.1144x + 0.7025
	5							y = 0.1144x + 0.7025
	5
	0
	0	10	20	30	40	50	60	70	80	90	100
					LOAD CAPACITANCE – pF

Figure 28. Typical Output Rise and Fall Time (10%–90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 2

	25					STRENGTH 3
	25				(VDD_IO = 3.3V)
					(VDD_IO = 3.3V)
–ns	20
TIMES	15
ALL	15
ALL
NDF	10			RISE TIME
EA	10		y = 0.1082x + 1.3123
EA			y = 0.1082x + 1.3123							FALL TIME
S										FALL TIME
RI									y = 0.0912x + 1.2048
	5								y = 0.0912x + 1.2048
	5
	0
	0	10	20	30	40	50	60	70	80	90	100
					LOAD CAPACITANCE – pF

Figure 29. Typical Output Rise and Fall Time (10%–90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 3

–30–

REV. 0

																		ADSP-TS101S
	25					STRENGTH 4											STRENGTH 7
	25					(VDD_IO = 3.3V)						25					STRENGTH 7
						(VDD_IO = 3.3V)						25					(VDD_IO = 3.3V)
AFDNAESRILLTIMES–ns												FALLANDRISETIMES–ns					(VDD_IO = 3.3V)
AFDNAESRILLTIMES–ns	20	y = 0.1071x + 0.9877										FALLANDRISETIMES–ns
												20
	15											15
												15
	10											10
		RISE TIME										10
		RISE TIME												RISE TIME
														RISE TIME
	5									FALL TIME		5	y = 0.0907x + 1.0071								FALL TIME
	5								y = 0.0798x + 1.0743												FALL TIME
																				y = 0.09x + 0.3134


	0											0
	0	10	20	30	40	50	60	70	80	90	100	0
	0	10	20	30	40	50	60	70	80	90	100	0	10	20	30	40	50	60	70	80	90	100
												0	10	20	30	40	50	60	70	80	90	100
					LOAD CAPACITANCE – pF											LOAD CAPACITANCE – pF
																LOAD CAPACITANCE – pF

	Figure 30. Typical Output Rise and Fall Time (10%–90%,	Figure 33. Typical Output Rise and Fall Time (10%–90%,
	VDD_IO = 3.3 V) vs. Load Capacitance at Strength 4	Figure 33. Typical Output Rise and Fall Time (10%–90%,
	VDD_IO = 3.3 V) vs. Load Capacitance at Strength 4	VDD_IO = 3.3 V) vs. Load Capacitance at Strength 7

	25					STRENGTH 5
	25					(VDD_IO = 3.3V)
						(VDD_IO = 3.3V)
–ns	20
LTIMES	15
FAL
AND	10
SE			RISE TIME
RI		y = 0.1001x + 0.7763								FALL TIME
	5	y = 0.1001x + 0.7763

									y = 0.0793x + 0.8691
									y = 0.0793x + 0.8691
	0
	0	10	20	30	40	50	60	70	80	90	100
					LOAD CAPACITANCE – pF

Figure 31. Typical Output Rise and Fall Time (10%–90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 5

	25					STRENGTH 6
	25					(VDD_IO = 3.3V)
						(VDD_IO = 3.3V)
–ns	20
LTIMES	15
FAL
AND	10
SE			RISE TIME
RI		y = 0.0946x + 1.2187								FALL TIME
	5	y = 0.0946x + 1.2187

									y = 0.0906x + 0.4597
									y = 0.0906x + 0.4597
	0
	0	10	20	30	40	50	60	70	80	90	100
					LOAD CAPACITANCE – pF

	15
						STRENGTH 0–7					0
						(VDD_IO = 3.3V)					0
						(VDD_IO = 3.3V)
–ns	10										1
VALID											2
VALID											3
OUTPUT											4
	5										5
	5										6
											6
											7
	0
	0	10	20	30	40	50	60	70	80	90	100

LOAD CAPACITANCE – pF

Figure 34. Typical Output Valid (VDD_IO = 3.3 V) vs. Load Capacitance at Max Case Temperature and Strength 0–71

1The line equations for the output valid versus load capacitance are: Strength 0: y = 0.0956x + 3.5662

Strength 1: y = 0.0523x + 3.2144

Strength 2: y = 0.0433x + 3.1319

Strength 3: y = 0.0391x + 2.9675

Strength 4: y = 0.0393x + 2.7653

Strength 5: y = 0.0373x + 2.6515

Strength 6: y = 0.0379x + 2.1206

Strength 7: y = 0.0399x + 1.9080

Figure 32. Typical Output Rise and Fall Time (10%–90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 6

REV. 0

–31–

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