Test Conditions

160

STRENGTH 5

The test conditions for timing parameters appearing in Table 19

on Page 23 include output disable time, output enable time, and

140

IOL

capacitive loading. The timing specifications for the DSP apply

120

VDD_IO = 3.45V, –40°C

mA

100

for the voltage reference levels in Figure 23.

80

–

VDD_IO = 3.3V, +25°C

60

NT

ER

40

UR

20

VDD_IO = 3.15V, +85°C

VDD_IO = 3.45V, –40°C

INPUT

)C

0

OR

1.5V

1.5V

IO

–20

VDD_IO = 3.3V, +25°C

OUTPUT

DD

–40

(V

–60

CE

VDD_IO = 3.15V, +85°C

–80

Figure 23. Voltage Reference Levels for AC

SOUR

–100

Measurements (Except Output Enable/Disable)

–120

IOH

–140

–160

–180

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

REFERENCE

SOURCE (VDD_IO) VOLTAGE – V

SIGNAL

Figure 20. Typical Drive Currents at Strength 5

tMEASURED_DIS

tMEASURED_ENA

tDIS

tENA

VOH (MEASURED)

VOH (MEASURED) – V

2.0V

STRENGTH 6

180

VOL (MEASURED) + V

1.0V

160

VOL (MEASURED)

IOL

140

tDECAY

tRAMP

–mA

120

VDD_IO = 3.45V, –40°C

100

80

VDD_IO = 3.3V, +25°C

OUTPUT STOPS

OUTPUT STARTS

60

NT

DRIVING

DRIVING

RE

40

VDD_IO = 3.45V, –40°C

HIGH IMPEDANCE STATE.

20

UR

VDD_IO = 3.15V, +85°C

0

TEST CONDITIONS CAUSE THIS

)C

–20

VOLTAGE TO BE APPROXIMATELY 1.5V.

IO

VDD_IO = 3.3V, +25°C

–40

DD

–60

Figure 24. Output Enable/Disable

V(

–80

VDD_IO = 3.15V, +85°C

E

OURC

–100

–120

Output Disable Time

–140

S

IOH

Output pins are considered to be disabled when they stop driving,

–160

–180

go into a high impedance state, and start to decay from their

–200

–220

0.5

1.0

1.5

2.0

2.5

3.0

3.5

output high or low voltage. The time for the voltage on the bus

0

to decay by ∆V is dependent on the capacitive load, CL and the

SOURCE (VDD_IO) VOLTAGE – V

load current, IL. This decay time can be approximated by the

Figure 21. Typical Drive Currents at Strength 6

following equation:

tDECAY

CL∆V

= ---------------

STRENGTH 7

IL

REV. 0

–29–