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DSP MicrocomputerT

ADSP-TS101S

KEY FEATURES

KEY BENEFITS

250 MHz, 4.0 ns Instruction Cycle Rate

Provides High Performance Static Superscalar DSP

6M Bits of Internal—On-Chip—SRAM Memory

Operations, Optimized for Telecommunications

19 19 mm (484-Ball) or 27 27 mm (625-Ball) PBGA

Infrastructure and Other Large, Demanding

Package

Multiprocessor DSP Applications

Dual Computation Blocks—Each Containing an ALU, a

Performs Exceptionally Well on DSP Algorithm and I/O

Multiplier, a Shifter, and a Register File

Benchmarks (See Benchmarks in Table 1 and Table 2)

Dual Integer ALUs, Providing Data Addressing and

Supports Low Overhead DMA Transfers Between

Pointer Manipulation

Internal Memory, External Memory, Memory-Mapped

Integrated I/O Includes 14 Channel DMA Controller,

Peripherals, Link Ports, Host Processors, and Other

External Port, Four Link Ports, SDRAM Controller,

(Multiprocessor) DSPs

Programmable Flag Pins, Two Timers, and Timer

Eases DSP Programming Through Extremely Flexible

Expired Pin for System Integration

Instruction Set and High Level Language Friendly DSP

1149.1 IEEE Compliant JTAG Test Access Port for

Architecture

On-Chip Emulation

Enables Scalable Multiprocessing Systems with Low

On-Chip Arbitration for Glueless Multiprocessing with

Communications Overhead

up to Eight TigerSHARC® DSPs on a Common Bus