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ADSP-218xN Series
Clock Signals and Reset
Table 15. Clock Signals and Reset
Parameter |
|
|
|
|
|
|
Min |
Max |
Unit |
|
|
|
|
||||||
Timing Requirements: |
|
|
|
||||||
tCKI |
CLKIN Period |
25 |
40 |
ns |
|||||
tCKIL |
CLKIN Width Low |
8 |
|
ns |
|||||
tCKIH |
CLKIN Width High |
8 |
|
ns |
|||||
Switching Characteristics: |
|
|
|
||||||
tCKL |
CLKOUT Width Low |
0.5tCK – 3 |
|
ns |
|||||
tCKH |
CLKOUT Width High |
0.5tCK – 3 |
|
ns |
|||||
tCKOH |
CLKIN High to CLKOUT High |
0 |
8 |
ns |
|||||
Control Signals Timing Requirements: |
|
|
|
||||||
tRSP |
|
Width Low |
5tCK1 |
|
ns |
||||
RESET |
|
||||||||
tMS |
Mode Setup before |
RESET |
High |
7 |
|
ns |
|||
tMH |
Mode Hold after |
RESET |
High |
5 |
|
ns |
|||
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
MODE A D
tMS 
tMH
RESET
tRSP
Figure 24. Clock Signals and Reset
REV. 0 |
–27– |