- •Performance Features
- •Integration Features
- •System Interface Features
- •Functional Block Diagram
- •GENERAL DESCRIPTION
- •Table 1. ADSP-218xN DSP Microcomputer Family
- •DEVELOPMENT SYSTEM
- •Additional Information
- •ARCHITECTURE OVERVIEW
- •Serial Ports
- •PIN DESCRIPTIONS
- •Memory Interface Pins
- •Table 3. Full Memory Mode Pins (Mode C = 0)
- •Terminating Unused Pins
- •Interrupts
- •LOW-POWER OPERATION
- •Power-Down
- •Idle
- •Slow Idle
- •System Interface
- •Figure 1. Basic System Interface
- •Clock Signals
- •Figure 2. External Crystal Connections
- •Reset
- •Power Supplies
- •Modes Of Operation
- •Setting Memory Mode
- •Passive Configuration
- •Active Configuration
- •IDMA ACK Configuration
- •Memory Architecture
- •Figure 3. ADSP-2184 Memory Architecture
- •Figure 4. ADSP-2185 Memory Architecture
- •Figure 5. ADSP-2186 Memory Architecture
- •Figure 6. ADSP-2187 Memory Architecture
- •Figure 7. ADSP-2188 Memory Architecture
- •Figure 8. ADSP-2189 Memory Architecture
- •Program Memory
- •Table 8. PMOVLAY Bits
- •Data Memory
- •Memory-Mapped Registers (New to the ADSP-218xM and N series)
- •I/O Space (Full Memory Mode)
- •Table 10. Wait States
- •Figure 9. Wait State Control Register
- •Composite Memory Select
- •Figure 11. System Control Register
- •Byte Memory Select
- •Byte Memory
- •Byte Memory DMA (BDMA, Full Memory Mode)
- •Figure 12. BDMA Control Register
- •Table 11. Data Formats
- •Internal Memory DMA Port (IDMA Port; Host Memory Mode)
- •Table 12. IDMA/BDMA Overlay Bits
- •Figure 13. IDMA OVLAY/Control Registers
- •Bootstrap Loading (Booting)
- •IDMA Port Booting
- •Bus Request and Bus Grant
- •Flag I/O Pins
- •Instruction Set Description
- •Designing An EZ-ICE-Compatible System
- •Figure 14. Mode A Pin/EZ-ICE Circuit
- •Target Board Connector for EZ-ICE Probe
- •Figure 15. Target Board Connector for EZ-ICE
- •Target Memory Interface
- •Target System Interface Signals
- •Specifications
- •ABSOLUTE MAXIMUM RATINGS
- •ESD Sensitivity
- •Power Dissipation
- •Table 13. Example Power Dissipation Calculation
- •Environmental Conditions
- •Table 14. Thermal Resistance
- •Test Conditions
- •Figure 16. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
- •Figure 17. Equivalent Loading for AC Measurements (Including All Fixtures)
- •Figure 18. Output Enable/Disable
- •Output Disable Time
- •Output Enable Time
- •Timing Specifications
- •General Notes
- •Timing Notes
- •Frequency Dependency For Timing Specifications
- •Output Drive Currents
- •Figure 19. Typical Output Driver Characteristics for VDDEXT at 3.6 V, 3.3 V, 2.5 V, and 1.8 V
- •Figure 20. Power vs. Frequency
- •Figure 21. Typical Power-Down Current
- •Capacitive Loading
- •Figure 22. Typical Output Rise Time vs. Load Capacitance (at Maximum Ambient Operating Temperature)
- •Clock Signals and Reset
- •Table 15. Clock Signals and Reset
- •Figure 24. Clock Signals and Reset
- •Interrupts and Flags
- •Table 16. Interrupts and Flags
- •Figure 25. Interrupts and Flags
- •Bus Request–Bus Grant
- •Table 17. Bus Request–Bus Grant
- •Figure 26. Bus Request–Bus Grant
- •Memory Read
- •Table 18. Memory Read
- •Figure 27. Memory Read
- •Memory Write
- •Table 19. Memory Write
- •Figure 28. Memory Write
- •Serial Ports
- •Table 20. Serial Ports
- •Figure 29. Serial Ports
- •IDMA Address Latch
- •Table 21. IDMA Address Latch
- •Figure 30. IDMA Address Latch
- •IDMA Write, Short Write Cycle
- •Table 22. IDMA Write, Short Write Cycle
- •Figure 31. IDMA Write, Short Write Cycle
- •IDMA Write, Long Write Cycle
- •Table 23. IDMA Write, Long Write Cycle
- •Figure 32. IDMA Write, Long Write Cycle
- •IDMA Read, Long Read Cycle
- •Table 24. IDMA Read, Long Read Cycle
- •Figure 33. IDMA Read, Long Read Cycle
- •IDMA Read, Short Read Cycle
- •Table 25. IDMA Read, Short Read Cycle
- •Figure 34. IDMA Read, Short Read Cycle
- •IDMA Read, Short Read Cycle in Short Read Only Mode
- •Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode
- •Figure 35. IDMA Read, Short Read Cycle in Short Read Only Mode
- •LQFP Package Pinout
- •100-Lead LQFP Pin Configuration
- •Mini-BGA Package Pinout
- •144-Ball Mini-BGA Package Pinout (Bottom View)
- •Outline Dimensions
- •144-Ball Mini-BGA (CA-144)
- •Ordering Guide
- •Table 29. Ordering Guide
ADSP-218xN Series
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
|
K Grade (Commercial) |
B Grade (Industrial) |
|
||
Parameter1 |
|
|
|
|
Unit |
Min |
Max |
Min |
Max |
||
|
|
|
|
|
|
VDDINT |
1.71 |
1.89 |
1.8 |
2.0 |
V |
VDDEXT |
1.71 |
3.6 |
1.8 |
3.6 |
V |
VINPUT2 |
VIL = – 0.3 |
VIH = + 3.6 |
VIL = – 0.3 |
VIH = + 3.6 |
V |
TAMB |
0 |
70 |
–40 |
+85 |
° C |
1Specifications subject to change without notice.
2The ADSP-218xN is 3.3 V tolerant (always accepts up to 3.6 V max VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH (max) approximately equals VDDEXT (max). This 3.3 V tolerance applies to bidirectional pins (D23–D0, RFS0, RFS1, SCLK0, SCLK1,
TFS0, TFS1, A13–A1, PF7–PF0) and input-only pins (CLKIN, RESET, BR, DR0, DR1, PWD).
ELECTRICAL CHARACTERISTICS
Parameter1 |
Description |
Test Conditions |
Min |
Typ Max |
Unit |
VIH |
Hi-Level Input Voltage2, 3 |
@ VDDEXT = 1.71 to 2.0 V, |
1.25 |
|
V |
|
|
VDDINT = max |
|
|
|
|
|
@ VDDEXT = 2.1 to 3.6 V, |
|
|
|
|
Lo-Level Input Voltage2, 3 |
VDDINT = max |
|
|
|
VIL |
@ VDDEXT 2.0 V, |
|
0.6 |
V |
|
|
|
VDDINT = min |
|
|
|
|
|
@ VDDEXT 2.0 V, |
|
0.7 |
V |
|
Hi-Level Output Voltage2, 4, 5 |
VDDINT = min |
|
|
|
VOH |
@ VDDEXT = 1.71 to 2.0 V, |
1.35 |
|
V |
|
|
|
IOH = – 0.5 mA |
|
|
|
|
|
@ VDDEXT = 2.1 to 2.9 V, IOH |
2.0 |
|
V |
|
|
= – 0.5 mA |
|
|
|
|
|
@ VDDEXT = 3.0 to 3.6 V, IOH |
2.4 |
|
V |
|
|
= – 0.5 mA |
|
|
|
|
|
@ VDDEXT = 1.71 to 3.6 V, |
VDDEXT – 0.3 |
|
V |
|
Lo-Level Output Voltage2, 4, 5 |
IOH = – 100 A6 |
|
|
|
VOL |
@ VDDEXT = 1.71 to 3.6 V, |
|
0.4 |
V |
|
|
Hi-Level Input Current3 |
IOL = 2.0 mA |
|
|
A |
IIH |
@ VDDINT = max, |
|
10 |
||
|
Lo-Level Input Current3 |
VIN = 3.6 V |
|
|
A |
IIL |
@ VDDINT = max, |
|
10 |
||
|
|
VIN = 0 V |
|
|
A |
IOZH |
Three-State Leakage |
@ VDDEXT = max, |
|
10 |
|
|
Current7 |
VIN = 3.6 V8 |
|
|
A |
IOZL |
Three-State Leakage |
@ VDDEXT = max, |
|
10 |
|
|
Current7 |
VIN = 0 V8 |
|
|
|
IDD |
Supply Current (Idle)9 |
@ VDDINT = 1.8 V, |
|
6 |
mA |
|
|
tCK = 12.5 ns, |
|
|
|
|
Supply Current (Dynamic)10 |
TAMB = 25° C |
|
|
|
IDD |
@ VDDINT = 1.8 V, |
|
25 |
mA |
|
|
|
tCK = 12.5 ns11, |
|
|
|
|
|
TAMB = 25° C |
|
|
|
REV. 0 |
–21– |
ADSP-218xN Series
ELECTRICAL CHARACTERISTICS (CONTINUED)
Parameter1 |
Description |
Test Conditions |
Min |
Typ Max |
Unit |
IDD |
Supply Current (Idle)9 |
@ VDDINT = 1.9 V, |
|
6.5 |
mA |
|
|
tCK = 12.5 ns, |
|
|
|
|
Supply Current (Dynamic)10 |
TAMB = 25° C |
|
|
|
IDD |
@ VDDINT = 1.9 V, |
|
26 |
mA |
|
|
|
tCK = 12.5 ns11, |
|
|
|
|
|
TAMB = 25° C |
|
|
A |
IDD |
Supply Current (Power- |
@ VDDINT = 1.8 V, |
|
100 |
|
|
Down)12 |
TAMB = 25° C |
|
|
|
|
Input Pin Capacitance3, 6 |
in Lowest Power Mode |
|
|
|
CI |
@ VIN = 1.8 V, |
|
8 |
pF |
|
|
|
fIN = 1.0 MHz, |
|
|
|
|
|
TAMB = 25° C |
|
|
|
CO |
Output Pin |
@ VIN = 1.8 V, |
|
8 |
pF |
|
Capacitance6, 7, 12, 13 |
fIN = 1.0 MHz, |
|
|
|
|
|
TAMB = 25° C |
|
|
|
1Specifications subject to change without notice.
2Bidirectional pins: D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–1, PF7–0. 3Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–FL0, BGH.
5Although specified for TTL outputs, all ADSP-218xN outputs are CMOS-compatible and will drive to VDDEXT and GND, assuming no dc loads. 6Guaranteed but not tested.
7Three-statable pins: A13–A1, D23–D0, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF7–PF0. 80 V on BR.
9Idle refers to ADSP-218xN state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
10IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 and Type 6, and 20% are idle instructions.
11VIN = 0 V and 3 V. For typical values for supply currents, refer to Power Dissipation section.
12See ADSP-218x DSP Hardware Reference for details.
13Output pin capacitance is the capacitive load for any three-stated output pin.
ABSOLUTE MAXIMUM RATINGS
Internal Supply Voltage (VDDINT)1 . . . . . . . . –0.3 V to +2.2 V
External Supply Voltage (VDDEXT) . . . . . . . . –0.3 V to +4.0 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
Output Voltage Swing3 . . . . . . . . . . .–0.5 V to VDDEXT +0.5 V
Operating Temperature Range . . . . . . . . . . .–40ºC to +85ºC
Storage Temperature Range . . . . . . . . . . . . –65ºC to +150ºC
Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . –280ºC
1Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2Applies to Bidirectional pins (D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–1, PF7–0) and Input only pins (CLKIN, RESET, BR, DR0, DR1, PWD).
3Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH).
–22– |
REV. 0 |
