- •Key Features
- •Key Benefits
- •Table Of Contents
- •Revision History
- •General Description
- •Dual Compute Blocks
- •Data Alignment Buffer (DAB)
- •Program Sequencer
- •Interrupt Controller
- •Flexible Instruction Set
- •DSP Memory
- •Host Interface
- •Multiprocessor Interface
- •SDRAM Controller
- •EPROM Interface
- •DMA Controller
- •Link Ports (LVDS)
- •Timer and General-Purpose I/O
- •Reset and Booting
- •Clock Domains
- •Power Domains
- •Filtering Reference Voltage and Clocks
- •Development Tools
- •Evaluation Kit
- •Additional Information
- •Pin Function Descriptions
- •Strap Pin Function Descriptions
- •ADSP-TS201S—Specifications
- •Recommended Operating Conditions
- •Electrical Characteristics
- •Absolute Maximum Ratings
- •ESD Sensitivity
- •Timing Specifications
- •General AC Timing
- •Link Port—Data Out Timing
- •Link Port—Data In Timing
- •Output Drive Currents
- •Test Conditions
- •Output Disable Time
- •Output Enable Time
- •Capacitive Loading
- •Environmental Conditions
- •Thermal Characteristics
- •576-Ball BGA_ED Pin Configurations
- •Outline Dimensions
- •Ordering Guide
ADSP-TS201S
OUTLINE DIMENSIONS
The ADSP-TS201S processor is available in a 25 mm × 25 mm, 576-ball metric thermally enhanced ball grid array (BGA_ED) package with 24 rows of balls (BP-576).
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25.20 |
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25.00 |
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24 |
22 |
20 |
18 |
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14 |
12 |
10 |
8 |
6 |
4 |
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2 |
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24.80 |
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23 |
21 |
19 |
17 |
15 |
13 |
11 |
9 |
7 |
5 |
3 |
1 |
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A |
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B |
1.25 |
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1.00 |
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C |
A1 BALL |
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D |
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1.00 |
BSC |
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E |
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INDICATOR |
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0.75 |
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F |
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G |
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H |
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23.00 |
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J |
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K |
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25.20 |
BSC |
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L |
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SQ |
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M |
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25.00 |
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N |
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P |
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24.80 |
1.00 |
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R |
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BSC |
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T |
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U |
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SQ |
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V |
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W |
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BALL |
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Y |
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PITCH |
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AA |
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AB |
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AC |
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AD |
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1.25 |
1.00 |
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25.20 |
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1.00 |
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BSC |
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25.00 SQ |
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0.75 |
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24.80 |
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TOP VIEW
DETAIL A
3.10 MAX
NOTES:
1.ALL DIMENSIONS ARE IN MILLIMETERS.
2.THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25 mm OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES.
3.THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10 mm OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.
4.CENTER DIMENSIONS ARE NOMINAL.
5.THIS PACKAGE CONFORMS WITH THE JEDEC MS-034 SPECIFICATION.
BOTTOM VIEW |
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1.60 MAX |
0.97 BSC |
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0.60 |
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0.50 |
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0.40 |
SEATING PLANE |
0.75 |
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BALL DIAMETER |
0.65 |
0.20 MAX |
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0.55 |
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DETAIL A
Figure 46. 576-Ball BGA_ED (BP-576)
ORDERING GUIDE
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Case Temperature |
Instruction |
On-Chip |
Operating |
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Part Number1, 2, 3, 4, 5 |
Range |
Rate6 |
DRAM |
Voltage |
Package |
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ADSP-TS201SABP-060 |
–40°C to +85°C |
600 MHz |
24M bit |
1.20 VDD, 2.5 VDD_IO, 1.6 VDD_DRAM |
(BP-576)7 |
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ADSP-TS201SABP-050 |
–40°C to +85°C |
500 MHz |
24M bit |
1.05 VDD, 2.5 VDD_IO, 1.5 VDD_DRAM |
(BP-576) |
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ADSP-TS201SWBP-050 |
–40°C to +105°C |
500 MHz |
24M bit |
1.05 VDD, 2.5 VDD_IO, 1.5 VDD_DRAM |
(BP-576) |
1 |
S indicates 1.xx/2.5 V supplies. |
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2 |
A indicates –40°C to +85°C temperature. |
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3 |
W indicates –40°C to +105°C temperature. |
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4 |
BP indicates thermally enhanced ball grid array (BGA_ED) package. |
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5 |
-060 indicates 600 MHz operation, and -050 indicates 500 MHz operation. |
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6 |
The instruction rate is the same as the internal processor core clock (CCLK) rate. |
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7 |
The BP-576 package measures 25 mm × 25 mm. |
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© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
D04324-0-11/04(0)
Rev. 0 | Page 44 of 44 | November 2004
