ADSP-TS201S
Link Port—Data Out Timing
Table 28 with Figure 18, Figure 17, Figure 19, Figure 20,
Figure 21, and Figure 22 provide the data out timing for the
LVDS link ports.
Table 28. Link Port—Data Out Timing
Parameter |
|
|
Min |
Max |
Unit |
|
Outputs |
|
|
|
|
|
|
tREO |
|
Rising Edge (Figure 18) |
|
200 |
ps |
|
tFEO |
|
Falling Edge (Figure 18) |
|
200 |
ps |
|
|
|
|
|
Greater of 2.0 or |
|
|
tLCLKOP |
|
LxCLKOUT Period (Figure 17) |
1, 2 |
1, 2 |
ns |
|
|
0.9 × LCR × tCCLK |
1.1 × LCR × tCCLK |
||||
tLCLKOH |
|
LxCLKOUT High (Figure 17) |
1 |
1 |
ns |
|
|
0.4 × tLCLKOP |
0.6 × tLCLKOP |
||||
tLCLKOL |
|
LxCLKOUT Low (Figure 17) |
1 |
1 |
ns |
|
|
0.4 × tLCLKOP |
0.6 × tLCLKOP |
||||
tCOJT |
|
LxCLKOUT Jitter (Figure 17)3 |
|
–/+ 125 |
ps |
|
|
|
|
|
Smaller of 2.54 or |
|
|
tLDOS |
|
LxDATO Output Setup, LCR = 1 and LCR = 1.5 (Figure 19) |
0.25 × LCR × tCCLK – 0.151, 2, 5 |
|
ns |
|
|
|
|
|
Smaller of 2.54 or |
|
|
|
|
LxDATO Output Setup, LCR = 2 and LCR = 4 (Figure 19) |
0.25 × LCR × tCCLK – 0.31, 2, 5 |
|
ns |
|
|
|
|
|
Smaller of 2.5 or |
|
|
tLDOH |
|
LxDATO Output Hold, LCR = 1 and LCR = 1.5 (Figure 19) |
0.25 × LCR × tCCLK – 0.151, 2, 5 |
|
ns |
|
|
|
|
|
Smaller of 2.5 or |
|
|
|
|
LxDATO Output Hold, LCR = 2 and LCR = 4 (Figure 19) |
0.25 × LCR × tCCLK – 0.31, 2, 5 |
|
ns |
|
|
|
Delay from LxACKI rising edge to first transmission clock |
|
|
|
|
tLACKID |
|
edge (Figure 20) |
|
1, 2 |
ns |
|
|
|
16 × LCR × tCCLK |
||||
tBCMPOV |
|
|
|
|
1, 2 |
|
|
LxBCMPO Valid (Figure 20) |
|
ns |
|||
|
|
2 × LCR × tCCLK |
||||
tBCMPOH |
|
|
Hold (Figure 21) |
3 × TSW – 0.51, 6 |
|
ns |
LxBCMPO |
|
|||||
Inputs |
|
|
|
|
|
|
|
|
LxACKI low setup to guarantee that the transmitter stops |
|
|
|
|
|
|
transmitting (Figure 21) |
|
|
|
|
|
|
LxACKI high setup to guarantee that the transmitter |
|
|
|
|
|
|
continues its transmission without any interruption |
|
|
|
|
tLACKIS |
|
(Figure 22) |
1, 2 |
|
ns |
|
|
16 × LCR × tCCLK |
|
||||
tLACKIH |
|
LxACKI High Hold Time (Figure 22) |
0.51 |
|
ns |
|
1 Timing is relative to the 0 differential voltage (VOD = 0).
2 LCR (link port clock ratio) = 1, 1.5, 2, or 4. tCCLK is the core period. Note that LCLK can be a maximum of 500 MHz (for example, if LCR = 1, then CCLK must be ≤ 500 MHz). 3 The –/+100 value applies for LCLKOUT = 500 MHz.
4 The 2.5 value for tLDOS applies for LCLKOUT ≤ 100 MHz. 5 The tLDOS and tLDOH values include LCLKOUT jitter.
6 TSW is a short-word transmission period. For a 4-bit link, it is 2 × LCR × tCCLK. For a 1-bit link, it is 8 × LCR × tCCLK ns.
tLCLKOP
VOD = 0V
LxCLKOUT
tLCLKOH tLCLKOL
tCOJT 
Figure 17. Link Ports—Output Clock
Rev. 0 | Page 31 of 44 | November 2004
ADSP-TS201S
VO_P
|
|
CL_P |
RL = 100 |
|
RL |
CL |
CL = 0.1pF |
||
|
||||
|
|
|
CL_P = 5pF |
|
VO_N |
|
|
CL_N = 5pF |
|
|
CL_N |
|
||
|
|
|
tREO |
tFEO |
+|VOD| MIN |
|
VOD = 0V |
|
–|VOD| MIN |
|
LxCLKOUT
VOD = 0V
tLDOS tLDOH tLDOS tLDOH
LxDATO
VOD = 0V
Figure 18. Link Ports—Differential Output Signals Transition Time |
Figure 19. Link Ports—Data Output Setup and Hold1 |
|
1 These parameters are valid for both clock edges. |
LxCLKOUT
VOD = 0V
LxDATO
VOD = 0V
tLACKID
LxACKI
tBCMPOV
LxBCMPO
Figure 20. Link Ports—Transmission Start
Rev. 0 | Page 32 of 44 | November 2004
ADSP-TS201S
FIRST EDGE OF 5TH SHORT WORD IN A QUAD WORD
LxCLKOUT
VOD = 0V
LxDATO
VOD = 0V
LxACKI
LxBCMPO
tLACKIS |
tBCMPOH |
LAST EDGE IN A QUAD WORD
tLACKIH
Figure 21. Link Ports—Transmission End and Stops
LAST EDGE IN A QUAD WORD
LxCLKOUT
VOD = 0V
LxDATO
VOD = 0V
tLACKIS |
|
tLACKIH |
LxACKI
Figure 22. Link Ports—Back to Back Transmission
Rev. 0 | Page 33 of 44 | November 2004
ADSP-TS201S
Link Port—Data In Timing
Table 29 with Figure 23 and Figure 24 provide the data in timing for the LVDS link ports.
Table 29. Link Port—Data In Timing
Parameter |
|
|
|
|
Min |
Max |
Unit |
Inputs |
|
|
|
|
|
|
|
|
|
|
|
|
Greater of 1.8 |
|
|
tLCLKIP |
|
|
LxCLKIN Period (Figure 24) |
1 |
|
ns |
|
|
|
or 0.9 × tCCLK |
|
||||
tLDIS |
|
|
LxDATI Input Setup (Figure 24) |
0.21 |
|
ns |
|
tLDIH |
|
|
LxDATI Input Hold (Figure 24) |
0.21 |
|
ns |
|
tBCMPIS |
|
|
|
|
1 |
|
|
|
|
LxBCMPI Setup (Figure 23) |
|
ns |
|||
|
|
2 × tLCLKIP |
|
||||
tBCMPIH |
|
|
|
|
1 |
|
|
|
|
LxBCMPI Hold (Figure 23) |
|
ns |
|||
|
|
2 × tLCLKIP |
|
||||
1 Timing is relative to the 0 differential voltage (VOD = 0). |
|
|
|
||||
|
|
|
|
|
FIRST EDGE IN FIFTH SHORT WORD IN A QUAD WORD |
|
|
|
LxCLKIN |
|
|
|
|||
|
VOD = 0V |
|
|
|
|||
LxDATI
VOD = 0V
tBCMPIS |
|
tBCMPIH |
LxBCMPI
Figure 23. Link Ports—Last Received Quad Word
tLCLKIP
LxCLKIN
VOD = 0V
tLDIS |
tLDIH |
tLDIS |
tLDIH |
||||
|
|
|
|
|
|
|
|
LxDATI
VOD = 0V
Figure 24. Link Ports—Data Input Setup and Hold1
1 These parameters are valid for both clock edges.
Rev. 0 | Page 34 of 44 | November 2004