Добавил:

Upload Опубликованный материал нарушает ваши авторские права? Сообщите нам.

Вуз:

Национальный исследовательский университет «МИЭТ»

Предмет:

[НЕСОРТИРОВАННОЕ]

Файл:

Chung-Yu Wu - Analog Circuit Design

.pdf

Скачиваний:

Добавлен:

05.06.2015

Размер:

29.49 Mб

Скачать

☆

<<< < Предыдущая 1 2 3 4 5 6 7 8 9 10 11 1213 / 4913 14 15 16 17 18 19 20 21 22 23 24 25 > Следующая >>>

									6 - 14
									CHUNG-YU WU
The numerator of H( s ) =		V2 ( s )	is g		( g		+ g		)( C R s +1)
The numerator of H( s ) =			is g	mi	( g	mg 1	+ g	mg 2	)( C R s +1)
		Vd ( s )		mi		mg 1		mg 2	c out
		Vd ( s )
Þ LHP Zero : -	1
Þ LHP Zero : -	Cc Rout
	Cc Rout

If Rout is large , LHP Zero may form a pole-zero doublet with Sp1’ or Sp2’

Þ very slow slew rate !!

If Rout is small , too large gm1 or gm2 is required.

Þ(large area ,large power)

Þlarge Cout. Freq. Resp. ↓

*Somehow difficult to design.

*Also the power dissipation of the buffer is large. (additional power dissipation)

§6-2.2 Adding Rc in series with Cc.

H( s ) =

can be solved.

Low frequency gain : Adm

= gmi (gmg 1 + gmg 2 )Ro Rd

LHP Poles :

SP 1 @

- 1

(unchanged)

(

+ gmg2

)

gmg1

Ro Rd Cc

SP 2

@ -

(gmg 1

+ gmg 2 )Cc

(unchanged)

Cd CL + Cc CL + Cd Cc

SP 3

@ -

Cd Cc + Cd CL +Cc CL

RC Cd CL Cc

æ LHP

gmg1

+ gmg 2

÷Zero : SZ = -

+ g

)-1]

ç RHP÷

mg1

mg 2

6 - 15

CHUNG-YU WU

1. If

or R =

: second-stage transconductance

m 2

gmg1 + gmg 2

gm2

® ±¥

No effect on the frequency response of the OP.

dominant pole Þ A (s ) @

Adm

Ado SP1

s + SP 1

P 1

SP1

For ω >> S

A ( jω ) =

Adm SP 1

A ( jω )

AdmSP1

jω

gmi

At ω ,

A ( jω

)

= 1 Þ ω

= A S

Large

Þ SP 2

» -

gmg 1 + gmg 2

For phase margin

~ 60

P 2

2 ~ 4,

gmg 1

+ gmg 2

= 2 ~ 4

ωu

gmi

@ 2 ~ 4 ,

CL @ Cc stable

gmg 1 + gmg 2

Gain

1) NMOS Realization :

-6 dB/octave

0 dB

VDD

f p1

f p 2

log(f)

-12 dB/octave

	-VSS
V1	V2	phase	log(f)
		0 o	log(f)
		- 45 o
		- 90 o
		- 135 o	- 180 o

I DS

μnCox

W [

-V2 -VTH )VDS -VDS

2 ]

2( VDD

¶I DS

−1

= ç

μn Cox

¶V

[2( V

-V

-V )]

ø V

DS =0

- VTH - body effect

( RC

)o =

RCmax

+ gmg 2

gmg 1

RCmin

Nonlinear Rc

V2min

V2max

(negative)

6 - 16

CHUNG-YU WU

Design R	c	:	(1) Design R , s.t.	( R )		=	1	(	1	)
					=0V
			c	c V2			gm 2		gmg1 + gmg 2

(2) At Rc= Rcmax or Rcmin ,

Sz must be large enough ! Otherwise, frequency performance will be degradated.

1) CMOS Realizations :

VDD

Mcn

Mcp

-VSS

-V

Consider the case in c.:

μnCox

[ 2(V − V −V )V −V

]

DSn

2 Ln

THn

DS DS

Rcn =

μn C ox

W n

[ 2( V DD − V2

− VTHn

)]

= μp Cox Wp

6 - 17

DSp

[ 2( V +V

-V

]

CHUNG-YU WU

THp

Rcp

μ pCox

Wp [ 2( V +V -V )]

THp

Rc −1 = ( Rcn // Rcp )−1 = Rcn −1 + Rcp −1

μn Cox

[ 2(VDD

− V2 − VTHn )] +

μp Cox

[ 2(V2

+ VSS − VTHp )]

μ pCox Wp

= β

n =

− 1

= β [ 2V

- 2V

+ 2V

-2V

] nearly indep. Of V2

THn

THp

−1

= g

mg1

+ g

mg 2

V2=0V

-1

V2min

V2max

2. If Rc	=	1 +( Cd +CL ) / CC
		gmg1 + gmg 2

Sz = Sp2 and pole-zero cancellation occurs.

Þ Sp3 >> Sp1 Þ AdmSp1 < Sp3 Þ stable

However, if the cancellation is not complete

Þ pole-zero doublet occurs ! Þ slow slew rate.

6 - 18

CHUNG-YU WU

§6-2.2 Feedforward compensation

Av3 is the gain of the source follower

A V3

+ Vout

Vin

-A V2

( 0 )( 1 +

)

v 3

1 LHP zero

Av 3

( 1 +

)

1 LHP pole

( 0 )( 1−

)( 1+

)

2 LHP poles

Av 2

v 2

1 RHP zero (CC)

( 1 +

)(1 +

)

1 LHP zero

z3 & z2 are generated from the Cgs of the source follower.

Vout

= A

( s ) = A

( s ) + A

( s )

VTOT

V 2

V 3

Vin

( 1+

)(1 +

)

z1'

z2'

z3'

= [AV 2 ( 0 ) + AV 3 ( 0 )]

( 1+

)(1 +

)

p1' : dominant pole

z1' , z2 ' , z3 ' : LHP Zeros

Design consideration : Any zeros below the unity-gain frequency must be placed as close as possible to their matching poles. This prevents the formation of any doublet !

z1' = p2 by adding CB1 and CB2(3.8pF) to control Cgs 9 + Cgs11

6 - 19

CHUNG-YU WU

Ref:IEEE JSSC , col SC-14, no.6 pp.1070-1077 , DEC.1979 Feedfoward +Miller(direct)

Ref:IEEE JSSC , col SC-15, no.6 pp.921-928 , DEC.1980

Feedfoward +Unity gain buffer + Miller

§6-3 Settling Behavior
	Vo			± 0.1%V or ± 0.01%V
				± 0.1%V or ± 0.01%V
	V
V − Io	g m1
	0	T S	TP	t
	0	T S	TP	TSET
	Slewing			Settling
	Period			Period

Slewing Period (Ts): Vo from 0V to V-Io/gm1 under voltage follower connection and worse case loading.(nonlinear operation)

Settling Period (TSET-Ts):

Vo from (V-Io/gm1) to ± 0.1% V or ± 0.01% V (quasi-linear operation) Settling Time (TSET): Ts +( TSET-Ts) = slewing period + settling period.

§6-3.1 Single-pole case

		CC
+ Input		Gain
-	Stage	Stage	Vo
	Io		Vo
	Io

~ differential-input to single-ended output converter

Slew rate:

6 - 20

CHUNG-YU WU

SR ≡

dVo

I o

|max Cc

ωu =

gmi

← single-pole case

SR =

I oωu

= ω

gmi

uCox

(

§6-3.1 Two-pole case

Ref IEEE JSSC vol.SC-17, no.1 pp.74-80, Feb. 1982

Ts = −	1	ln[1 −		gm 1	( V −	I o	)	Fig.2

	ω1			I o ao		gm1
approximation e− ω 1TS 1 − ω T								=> eq.(19) conventional expression
						1 S
After Ts Vo= V-Io/gm1						Input voltage = V-( V-Io/gm1) = Io/gm1
						=> enter the linear (or quasi-linear) region
Feedback Function for unity-gain voltage-follower connection
=> A( s ) =			a( s )			eq.(20)-(23)
			+ a( s )
1

two poles S = −ξω n ±

eq.(24)

ξ =

ω1 + ω2

− 1ωn

2ωn

(double negative real poles)

damping ratio

= 1 critically damped

< 1 underdamped

ξ > 1 overdamped

(complex conjugate poles)

(real and negative pole)

ξ =

ω + ω

ω 2

gm 2 / c2

(CC, C2 >> C1)

2ω n

2 aoω1

2 ωu

2 gm 1 / cc

6 - 21

CHUNG-YU WU

ξ	1	=> CC		4( gm1 )C2	(CC, C2 >> C1)
				gm 2
		=>	ω2	4ωu ω2 = 2 ~ 4		ω 2 < 4ω u	underdamped
		=>	ω2	4ωu ω2 = 2 ~ 4		ω 2 > 4ω u	overdamped
				ωu
(1) Underdamped: TS eq. (14) or (19)					max.overshoot: eq.(36)
			TP eq. (35), (33)		settling time: eq.(40),(39)
(2) Critically Damped				Vo(t): eq.(41)
				TSET : eq.(43)
				V
					0.001
				TS	TSET	t

(3) Overdamped TSET : eq.(47)

Simulation & Calculation : Fig.7, Fig.8

Further references:

(1)IEEE JSSC, vol. SC-18, pp.389-394, Aug. 1983

(2)IEEE JSSC, vol. SC-21, pp.478-483, June. 1986

6 - 22

§6-4 Slew rate of CMOS OP AMPs

§6-4.1 Two-stage OP AMPs

CHUNG-YU WU

Two poles:

S p1 , S p 2 ,

S p 1

S p 2

S p1

<<ωu <<

Sp 2

,Vout ( s ) = gmiVin ( s ) / sCc

Vout

( jw )

Vin ( jw )

jwCc

ω =ωu ,

Vout

Vin

Þ ω

gmi

or C

= g

/ ω

The slew rate SR =

dVout

max

= I

/ C

ICωu

= ω

gmi

2uCox(W / L )i

ωu -, Io -,( W / L )i ¯ Þ SR −

* Io / CL

³ I o / CC or CL

dVout

£ CC

dVout

( = I o )

Slew rate enhancement and degradation

Vin

V1	degradation

	-	Vo
	+	Vo
	+

Vin

enhancement

6 - 23

(1) Positive step

CHUNG-YU WU

+ VDD

off

Io + iw

off

Io + iw

vout

off

~ vin

- VSS

dvω

( t )

Cω

dvin ( t )

iω ( t ) = Cω

vout( t ) = C ò( I o + iω )dt = C

+ C

= I o t + Cω V1u( t ) CC CC

(2) Negative step

	+ VDD
	M	M4
	3	on			Io + iw
	on	on			Io + iw
		Io	- iw		CC
					CC
	Io- iw			-	vout
				+
-	on	off	+
	vw	M2	+	V1
	M1	M2	+	V1
	Cw	Io	~ vin
	iw	Io	-
	iw		-
		- VSS

<<< < Предыдущая 1 2 3 4 5 6 7 8 9 10 11 1213 / 4913 14 15 16 17 18 19 20 21 22 23 24 25 > Следующая >>>

Соседние файлы в папке different

#
05.06.2015208.9 Кб295-1.doc
#
05.06.2015107.52 Кб295.doc
#
05.06.20158.56 Mб29Advanced Mathematical Methods for Scientists and Engineers.pdf
#
05.06.20152.23 Mб33Allen&Holberg - 10+11.pdf
#
05.06.20152.21 Mб49Allen&Holberg - Analog CMOS Circuit Design.pdf
#
05.06.201529.49 Mб49Chung-Yu Wu - Analog Circuit Design.pdf
#
05.06.20151.84 Mб34Structure and Interpretation of Signals and Systems (E. (1).djvu
#
05.06.20151.84 Mб28Structure and Interpretation of Signals and Systems (E.A.Le.djvu
#
05.06.20154.49 Mб35System on a Chip Verfication_Methodology and Techniques.pdf
#
05.06.20151.33 Mб49АИС-1 (до ОУ).doc
#
05.06.2015797.7 Кб47АИС-2 (ОУ).doc