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Национальный исследовательский университет «МИЭТ»

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Chung-Yu Wu - Analog Circuit Design

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6 - 4

CHUNG-YU WU

GLeq=gds1+gds2+gm2+gmb2

CLeq=Cdb1+Cgs2+Csb2+CL

Applying the Miller's theorem, we have

				Vo
Vin	RS	G	C	C
	Cin	G	C	C
		Leq	Leq+	gd1
		(gm1-sCgd1)V1

Cin=Cgs1+Cgd1(1+gm1/GLeq)

Gs (sC gd1 - gm1)>Av(s) @ [ ]

(sC in + Gs ) s(C Leq + Cgd1) +CLeq

*Right-Half-Plane Zero Sz = gm1/Cgd1

*Left-Half-Plane Poles Sp1= Gs/Cin (input pole)

Sp2= GLeq/(CLeq+Cgd1) (output pole).

If Cgd1 and CLeq are small >Sp1 is the dominant pole.

*If CL is large, the dominate pole is Sp2 (gm2+gmb2)/CL

*The input impedance can be approximated by

Zin@				1					near the upper 3dB frequency.
Zin@								ù	near the upper 3dB frequency.
é			+(1+ g		1			ù
	C				1	)C		s
	C			m1 G Leq		)C		s
êê		gs1		m1 G Leq			gd1	úú
ë								û

* The exact Zin is

(Cgd1 +CLeq )s

G Leq

Zin Cgs1s|| ê

êC

(1+ g

gd1s

Leq

G Leq

(Cgd1

+ CLeq )s

<<1 and

Cgds1s

(1+gm

G Leq

Zin can be approximated by the previous formula.

6 - 5

§ 6-1.3 Cascode amplifer stage

CHUNG-YU WU

					Cdb2
+VDD						+
		RS	V1	Cgd1	-gm2V2	V3	Cgs3	gm3V3
		RS	V1	Cgd1	-gm2V2	_
				Cdb1	Cgs2+			Vo
M3	Vin	Cgs1		gm1V1	Cgs2+	Cgd2	Csb3	CL
M3	Vin	Cgs1		gm1V1	Csb2		Csb3	CL
	Vo			rds1	Csb2

VBIAS

Vin

1/g2

gm2V2

CLeq 1/gm3

(gm1-s Cgd1)V1

Vin

rds2, rds3, gmb2, gmb3 are neglected.

-VSS

= gm 2

rds1

= Cgs1

+ (1 +

gm 1

)Cgd1

g m 2

= Cgd1 +Cdb1 + Cgs2

+Csb2

CLeq = CL + Cgd 2 +Cdb2 + Csb3 +Cgs3

A v

(s) =

- Gs gm 2 (sCgd1 -gm 1 )

(sC1 +G s )(sC 2 + g2 )(sC Leq

+ gm 3 )

RHP Zero:Sz =

gm1

Cgd1

LHP Pole :Sp1

= -

; Sp 2

= -

; Sp 3 =

- gm 3

CLeq

Sp1 usually is the dominant pole.

Þ f 3dB @

Sp1

2pC1

* Typically, gm 1 = g m 2 ,then C1 = Cgs1 + 2Cgd1

§6-1.4	CMOS gain stage								6 - 6
§6-1.4	CMOS gain stage								CHUNG-YU WU
	+VDD					Cgd2			CHUNG-YU WU
	+VDD				V1	Cgd2
							gm2V1
						Cgs2		gds2		Cdb2
RS	M2	Vo		RS
RS				RS
					V1	Cgd1
					V1	Cgd1				Vo
Vin	M1	CL	Vin				gm1V1
						Cgs1		gds1	Cdb1	CL
						Cgs1			Cdb1	CL
	-VSS
		RS		Cgd1+ Cgd2
					(gm1+ gm2)V1			Vo
Vin				Cgs1+ Cgs2	(gm1+ gm2)V1		GLeq	CLeq
Vin				Cgs1+ Cgs2			GLeq	CLeq
		RS	V1
			V1					Vo
				[gm 1+ g m 2-s(Cgd1+Cgd2)]V1				Vo
				[gm 1+ g m 2-s(Cgd1+Cgd2)]V1
Vin				Cin			GLeq	CLeq+Cgd1+Cgd2
			G Leq	= gds1 + gds2	CLeq	= Cdb1 + Cdb2 + CL

Cin = Cgs1 + Cgs2 + (1+ gm1 + g m 2 )(Cgd1 + Cgd2 )

G Leq

Av (s)

G s [s(Cgd1 + Cgd 2 ) − (gm 2 + gm 2 )]

[s(Cgd1 + Cgd2 + CLeq ) + G Leq ](sC in + G s )

RHP Zero:Sz = gm 1 + gm 2

Cgd1 + Cgd2

LHP Poleo:Sp1 = − G s

Cin

Sp 2 = −

G Leq

Cgd1 + Cgd2 + CLeq

If Rs is large enough ( Rs is the output resistance of the preceding stage),

Sp1 << Sp2

Sp1 is the dominant pole.

§6-1.5	CMOS differential amplifier								6 - 7
§6-1.5	CMOS differential amplifier								CHUNG-YU WU
1.Differential-mode half circuit									CHUNG-YU WU
1.Differential-mode half circuit
			Cgd1
	+						rds4\|\|rds1	+
								+
1 Vid			1 gm1Vid
1 Vid		Cgs1	1 gm1Vid			CLeq		1 V
2			2					2	od
									od
	_							_
	_
			CLeq º CL + Cdb4 + Cdb1
		+VDD				+VDD
VBIAS					M3		M4	VBIAS1
VBIAS		M4						VBIAS1
		M4
			1 V		CL		CL
1 V			2	od
			2

2	id					M2	M1
2		M1				M2	M1
		M1
					VBIAS2
		-VSS

-VSS

1- s

Cgd1

Vod

gm1

gm 1

A d

= H (s) = -

gds4 + gds1

CLeq

+ Cgd1

Vid

ê1

)s ú

gds4

+ gds1

RHP Zero:f z

gm 1

fz >fp

|Ad|

2pCgd1

-60db/Octave

LHP Pole:f p

gds4

+ gds1

2p(Cdb4 + Cdb1 +CL

+Cgd1 )

fu A0f p =

gm 1

fu fz

2p(Cdb4 +Cdb1

+CL + Cgd1 )

2.Common-mode half circuit:

(gds4 + sCM )Voc + gds1 (Voc - Vs ) +gm 1 (Vic

-Vs ) +Cgd1s(Voc - Vic ) = 0

6 - 8

Cgd5 + Cdb5 + Csb1

CHUNG-YU WU

(V - V

) + V (

s) -g

- V ) - C

s(V - V ) = 0

ds1

gs1

ds5

V [

+ C

)s + C s] = -[g

+sC

]V + (C

s +C

s)V

2rds5

gd5

db5

sb1

gs1

ds4

gd1

gs1

gd1

V = -

[gds4 +sC M

+ sCgd1 ]Voc -(Cgs1s +Cgd1s)Vic

Cgd5 +Cdb5 + Csb1

s +C

ê2r

gs1

ds5

+VDD

Vic

Cgd1

Voc

VBIAS1

Voc

gm1(Vic-Vs)

Cgs1

gds1

gds4

Vic

(Csb1+Cgd5+Cdb5)/2

2/gds5

VBIAS2

2M5

CM=CL+Cdb4+Cdb1

-VSS

gmb1 is neglected

Þ A c (s) = Voc

-Cgd1 ( Cgd5 +Cdb5 + Csb1

+ Cgs1 )s2 +[( Cgd5 + Cdb5 +Csb1

+Cgs1 )gm1

= -

+ Cdb5

+Cdb5 + Csb1

Cgd5

+ Csb1

+ Cgs1 )(CM + Cgd1 )s

Cgd5

+ Cgs1 )

(

2 +[(

Cgd1 - (gds1 + gm 1 )(Cgs1

+ Cgd1 )]s +

gm1

2rds5

+Cgd1

+ (CM

+ Cgd1 )(gds1 + gm1 )]s +

ds1 + (gds1 +g m1 )gds4

(gds4 +gds1 ) +

2rds5

ds4

2rds5

Solve the pole-zero position : Þ 1 RHP zero, 1 LHP zero,2 LHP poles

fZR

fZL

fp1

fp2

fZR >> fZL

(Cgd5+Cdb5+Csb1)/2

fZL

fp2

fp1 < fp2

CMRR

Load pole

tail pole

CMRR

degradation region

6 - 9

CHUNG-YU WU

§6-1.6 CMOS differential-input-to-single-ended output converter

Vi = Vid + Vic Vo = Vod + Voc		+VDD
The hail-circuit method cannot be used in		+VDD
The hail-circuit method cannot be used in
the high frequency analysis.		M4	M3
Two unequal signal paths to the output			E
Two unequal signal paths to the output
Þ Load path and tail path			CE	Vo
Þ Both Cs and CE appears in the Ad(s)			Load	CLeq
expression.				CLeq
expression.		M1	M2
There are two dominate poleo in Ad.	Vin	M1	M2
There are two dominate poleo in Ad.	Vin		Tail
gds1 + gds4			Tail
gds1 + gds4
Output pole Wp1		Io
CLeq	Ro	Io	CS

Mirror pole

Wp2

gm 34

-VSS

Tail path:A1

(s) =

Wp1

Load path: A2 (s) =

A 0

(1 +

)(1 +

)

Wp1

Wp 2

(2 +

)

Ad (s) = A1 (s)As (s) =

Wp 2

(1 +

)(1 +

)

Wp1

Wp2

LHP zero: W

2gm 34

= 2W

Approximate analysis:

The dominant pole of

(s)

is Sp1 = −

gds1 + gds4

(output pole)

CLeq

Ad (s)

gm1

sC Leq

+ (gds1 + gds4 )

(

) + sCs

gds1

The A c (s) can be written as

Ac (s) −

2gm 4

sC Leq +(gds1 + gds4 )

The dominant pole of A c (s)

Sp1 = −

gds1 + gds4

CLeq

But the left-half-plane zero is

SzL

= −

(

)

R 0

The CMRR (≡ A d ) is degradated by 20dB/decade at high frequency. A c

6 - 10

CHUNG-YU WU

§6-2 Frequency Compensations

+VDD

Ml1

Ml2

Mg1

Ms1

gdsl+gdsi

gdsgl+gdsg2

Mi1

Mi2

vi1

vi2

Mg2

VBIAS

Ms2

-VSS

Without CC

SP 1

= − 1 ( gdsl + gdsi )

, SP 2

= − 1 ( gdsg1

+ gdsg 2 )

gmg1+gmg2

Cd CL

equivalent

gmi(vi1-vi2)

gdsl+gdsi

gdsg1+gdsg2

circuit

=gmivd

≡ v

− v

i 1

i 2

6 - 11

CHUNG-YU WU

H ( s ) =

v 2

vi1

− vi 2

+ g mi ( gmg1 + gmg 2 )Rd Ro ( 1 −

sCC

)

g mg1 + gmg 2

1 + s[( C

+ C

)R + ( C

+ C

( g

mg1

+ g

mg 2

)R R ] + ( C

+ C

)R R

O d

where

º -

gdsg1 + gdsg 2

gdsl + gdsi

» -

CC ( gmg1 + gmg 2 )

Sp 1

Sp 2

( gmg1 + gmg 2 )RO Rd CC

CO CL + Cd CL + Cd CC

Sz '

gmg 1 + gmg 2

à RHP Zero

gain dB

RHP zero

f p1

f z '

f p 2'

log(f)

phase

0 o

- 45 o

- 180 o

- 135 o

Þ Phase margin is not

large enough

log(f)

Feedforward effect on

ICC

How to solve this problem ?

If I CC

=( gmg 1 + gmg 2 )Vd ,

I o

= 0 and V2 = 0

(gmg1+gmg2)v

Þ A zero is formed.

6 - 12

CHUNG-YU WU

§6-2.1 Using a unity-gain buffer in the feedback path

Unity Gain

Buffer

V1	V	2
		2

	+
CC	~ V2
V1	-
V1	V	2
		2

Isolate node 1 from node 2 to prevent feedforward.

Keep the Miller effect unchanged.

Source follower can act as a unity gain buffer.

g V +

+ C sV + (V −V )C

s = 0

--------- (1)

+ g

)V +

V + C

= 0

--------- (2)

mg1

mg 2

H( s ) =

gmi( gmg1 + gmg 2 )

1 + s[R

+ R ( C

+ C

) + C

( g

mg1

+ g

mg2

)R R ]+ ( C

+ C

o d

Sp1

≈ −

(unchanged)

(gmg1 + gmg 2 )Ro Rd Cc

Sp 2

≈ −

Cc ( gmg 1 + gmg 2

)

RHP Zero has be eliminated.

CcC L +Cd CL

6 - 13

CHUNG-YU WU

Actual Circuits :

1	VDD		2		VDD
	VDD				VDD
	M1	VBIAS			M1
		VBIAS
				CC
	CC			CC		V2
						V2
						VBIAS or
V1	M2		V1		M2	connected to the
	M2				M2	output
		V2				output
		V2
	-VSS				-VSS
					Cgs1	V2
						V2
		CC			Cout
	1 2 Þ	Rout			Cout
	1 2 Þ	V1				C +C
						L gd1

- αV2

Cgs1 may introduce a RHP zero. But usually this RHP zero is large.

Cgs1 is very small.

»(

)

out

gm1

gm 2

g V

+ C sV + (V − αV

)(

)−1 = 0

mi d

Cc s

+ Couts

Rout

³ C

Rout

out

ö−1

Cc s

Þ ç

ç Cc s

+ Cout s ÷

Cc Rout s + 1

Rout

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