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Allen and Holberg - CMOS Analog Circuit Design

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Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-4

GAIN OF THE TWO-STAGE COMPARATOR

		+			+
		+
gm1vid	r ds2	r ds4 v1 gm6v1	r ds6	r ds7	vout
		-			-
					-

vid = vP - vN

		gm1			gm6
	Av =
	gds2 + gds4 gds6 + gds7
			W1W6
	Av =	2 KNKP L1 L6
	Av =	λ2 + λ4 ) ( λ6 + λ7 ) I1I6
	(	λ2 + λ4 ) ( λ6 + λ7 ) I1I6
Using	W1	W6	λN = 0.015V-1, λP = 0.02V-1
Using	= 5,	= 5,	λN = 0.015V-1, λP = 0.02V-1
	L1	L6
and Table 3.1-2 values;
	Av =	2 (17)(8)(5)(5)			.10-6	95199.10-6
	Av =				.10-6	=
	(0.015+0.02)2			I1I6		I1I6

Assume I1 = 10 µA and I6 = 100 µA

Av = 3010

VOH - VOL = Resolution = 5 mV (assume)

then VOH - VOL = 1000 . 3000 = 15 Volts

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-5

PROPAGATION DELAY OF THE TWO-STAGE COMPARATOR

				VDD
						signal swing
						less than the
	M3				M4			output
									+
								VGS6
									-	M6
										M6
vN	M1			M2				vP		i6 key node
									CL1	vO
										i7
VBIAS			M5							CL2
			M5							M7
			i5							M7
			i5
		VSS
	V	GS6	= V	DD	- v		P	+ V
		GS6		DD			P		D G 2

dv
iC = C dt	, t =
v
C I
	t2+
V	VTRP3
VSSDD
	VTRP3
	t2-

	VTRP3 - VS S
t2+ = CL2 K P W6		- \|VT6 \|) 2
	2 L6 ( V D D - vP - VD G 2	- \|VT6 \|) 2	- I7

VDD - VTRP3

t2- = CL2 W7 L5

L7 W5 i5

Slew rate = isource/sink CLi

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-6

CALCULATION OF COMPARATOR PROPAGATION DELAY

Find the total propagation delay of the comparator shown when the input vP goes from -1 to +1 in 2ns. Assume the trip point of the output(next stage) is zero.

Total delay = 1st stage + 2nd stage

	delay	delay
t =	t1 + t2
t1 =	( vDO(t0) - VTRP2)
t1 =	I5	CL1 ,
	I5

	+5V
10
10	M4	40
M3	M4	10
	CL1=0.3pF		M6
	vDO		M6
vN M1	M2		I6
vN M1	M2		vO
20		vP	vO
10		vP	CL2=
			10pF

I5=20 A I7=40 A

-5V

vDO(t0) = 5 because vP = -1V

VTRP2 = VDD

- VGS6, VGS6 = |VT6| +

2I7

KP'( W6/L6)

VGS6 = 1 +

2.40

= 2.58 V ‘ VTRP2 = 5 - 2.58 = 2.42 V

8.4

0.3pF

t1 = (5 - 2.42)

= 38.7ns

20µA

t2 = vO (t

CL2

0) - 0

= 5

I6 - I7

KP6' W6

- V

(min) - V

D D

D O

2 L6

[VDO(min) is an optimistic assumption based on vDS2 ≈ 0]

VDO(min) ≈ vDS2(≈0) - vGS1 + vN = -VT1 -					I5	= -1.77
VDO(min) ≈ vDS2(≈0) - vGS1 + vN = -VT1 -					KN.2	= -1.77
I6 =	8.10-6			µA
I6 =	2	(4)(5 - (-1.77) -1) 2 = 533		µA
	2	10 pF
t2 = 5		10 pF	= 101 ns
t2 = 5		(533 - 40) µA	= 101 ns
t = t1 +		t2 ≈ 139 ns

Second order consideration: Charging of Csb of M1 and M2

Allen and Holberg - CMOS Analog Circuit Design Page VI.3-7

SIMULATION OF THE PROPAGATION DELAY

5 v

			+5V
		10
	M3	10	M4
	M3		M4	M6
			(6)	M6	40
			(6)		10
			CL1		10
vN	M1		CL1		(9)
vN	M1	20	M2		(9)	vO
3 v		20	vP			vO
3 v		10	vP		CL2
		10			CL2
2.42v	M8	10			20
	M8	10			20
				M7	10
			-5V		V(9)
1 v			vP

0v tprop=167 ns

Actual

-1 v

-1.54v

Approx.

-3 v

-5 v
0ns	50ns	100ns	150ns

V(6)

COMPARATOR PROPAGATION DELAY VDD 10 0 DC 5V

VSS 11 0 DC -5V VN 1 0 DC 0V

VP 2 0 PULSE(-1 1 0N 1N 1N 500N 1U) M1 3 1 5 5 MNMOS W=20U L=10U M2 6 2 5 5 MNMOS W=20U L=10U M3 3 3 10 10 MPMOS W=10U L=10U M4 6 3 10 10 MPMOS W=10U L=10U M5 5 8 11 11 MNMOS W=10U L=10U M6 9 6 10 10 MPMOS W=40U L=10U M7 9 8 11 11 MNMOS W=20U L=10U M8 8 8 11 11 MNMOS W=10U L=10U CL1 6 0 0.3PF

CL2 9 0 10PF IS 0 8 DC 20UA

.MODEL MNMOS NMOS VTO=1 KP=17U +LAMBDA=0.015 GAMMA=0.8 PHI=0.6

.MODEL MPMOS PMOS VTO=-1 KP=8U +LAMBDA=0.02 GAMMA=0.4 PHI=0.6

.TRAN 2N 300N

.PRINT TRAN V(6) V(9) V(2)

.PROBE

.END

200ns

250ns

300ns

Time

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-8

SMALL SIGNAL PERFORMANCE

+	+gm1	gm2
vin	+gm1	gm2	+
-	-		+
	R1 C1	R2 C2	vout

vout(s)	Aoωp1ωp2
vin(s)	= ( s + ω p 1) ( s + ω p 2)

ωp1 = 1 R1C1

ωp2 = 1 R2C2

Ao = gm1gm2R1R2

Example - (Fig 7.3-4)
1	1
I5 = 20µA ‘ R1 = gds2 + gds4	= 10µA = 3.33MΩ
1
ωp1 = (0.3pF)(3.33MΩ) = 1Mrps
1	1
I7 = 40µA ‘ R2 = gds6 + gds7	= 40µA(.03)	= 833KΩ
1
ωp2 = (10pF)(833KΩ)	= 120Krps
gm1 = 26µs, gm2 = 50.6µs ‘	Ao = 1099

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-9

TWO-STAGE, CMOS COMPARATOR

General Schematic

VDD

VSS

Key Relationships for Design:

G S

- V

(sat) =

(sat)]2

vDS(sat) =

2iD(sat)

Also,

g m = 2βID

where

β = KW L

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-10

COMPARATOR DESIGN PROCEDURE

1. Set the output current to meet the slew rate requirements.

dV i = C dt

2. Determine the minimum sizes for M6 and M7 for the proper ouput

voltage swing.

vDS(sat) =	2ID
	β

3.Knowing the second stage current and minimum device size for M6, calculate the second stage gain.

-gm6

A2 = gds6 + gds7

4.Calculate the required first stage gain from A2 and gain specifications.

5.Determine the current in the first stage based upon proper mirroring and minimum values for M6 and M7. Verify that Pdiss is met.

6.Calculate the device size of M1 from A1 and IDS1.

A1	=	-gm1		and gm1	=	2K'W/L
		gds1	+ gds3			IDS1

7.Design minimum device size for M5 based on negative CMR requirement using the following (IDS1 = 0.5IDS5):

vG1(min) = VSS + VDS5			+	IDS5
vG1(min) = VSS + VDS5			+	+ VT1(max)
				β1
where VDS5	=	2IDS5	= VDS5(sat)
where VDS5	=	β5	= VDS5(sat)
		β5

8.Increase either M5 or M7 for proper mirroring.

9.Design M4 for proper positive CMR using:

vG1(max) = VDD -	IDS5	(max) + VT1
vG1(max) = VDD -	- VTO3	(max) + VT1
	β3

10.Increase M3 or M6 for proper mirroring.

11.Simulate circuit.

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-11

DESIGN OF A TWO-STAGE COMPARATOR

Specifications:
Avo > 66 dB				Lambda = 0.05V-1 (L = 5 µm)
Pdiss < 10 mW			VDD = 10 V
CL = 2 pF				VSS = 0 V		K'W
tprop < 1 µs				Recall that β =		K'W
							L
CMR = 4-6 V
Output swing is VDD - 2V and VSS + 2V
1). For tprop << 1 µs choose slew rate at 100 V/µs
dvOUT		= ( 2.10-12) ( 100.10-6) = 200 µA
I7 = CL	dt	= ( 2.10-12) ( 100.10-6) = 200 µA
	dt
2). Size M6 and M7 to get proper output swing,
M7:
2V > vDS7(sat) =			2I7	=	2(200µA)			→		W7	> 5 . 88
2V > vDS7(sat) =			β7	=	17.0µA/V2(W7/L7)			→		L7	> 5 . 88
M6:
		2( IOUT+I7)			2(400µA)					W
					2(400µA)				→	6
2V > vDS6(sat) =			β6	=	8.0µA/V2(W6/L6)				→	L6	> 12 . 5
-gm6			-1		2KP'W6		≈ -10
3). A2 = gds6 + gds7		=	λN + λP		I6L6		≈ -10

4). Avo = A1A2 = 66 dB ≈ 2000 → A1 = 200

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-12

COMPARATOR DESIGN - CONT'D

5). Assuming vGS4 = vGS6, then I4

choose S4 = 1 which gives I4 = 12.5 (200µA)

= 16.0 µA

200µA

µA

Assume S5 = 1 which gives I5 = S

5.88

= 34

= 17 µA

and I4 = 2 I5

Choose

I4 = 1 7 µA

to keep

ratios greater than 1.

I5 = 34 µA

W6 17

= L6

200

= 1.06 ≈ 1.0

Pdiss = 10( I7 + I5 ) = 2.34 mW < 10 mW

6). A1

1 →

1 = [ (λ1 + λ4)A1]

λ1

= 200

+ λ4

I4L1

2KN'

W1 = 2 0 0

(Good for noise)

7). VDS5 = vG1(min) - VSS

- VT1(max)

β1

VDS5 = 4 - 0 -

(34)

-1 = 2.90 V

2(17.0)(200)

2I5

2(34µ)

VDS5 =

β5

(17µ)S5 →

> 0.48

= 1.0 →

8). S5 = I7 S7 = 200 (5.88)

= 1 . 0

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-13

COMPARATOR DESIGN - CONT'D

9). VG1(max) = VDD -

- VTO3 (max) + VT1(min)

β3

β3 =

V D D - VG1 (max) -

VTO3 (max) + VT1(min)

34 µA

= 2.76.10-6

1 0 - 6 - 1 + 0 . 5) 2

(

= (2.76)(2)

= 0.69

W4 > 0.69

(Previously showed

> 1.06

so no modification is necessary)

10). Summary

Wdrawn

(L - 1.6)

Design Ratios

Actual Values with 5 m

Proper Mirroring

minimum geometry

and LD = 0.8 m

1000

680

= L2

= 200

= L2

3.4

‘

= L4

= 1.0

= L4

= 1.0

3.4

‘

= 12.5

62.5

= 5.88

↑

(Need to adjust for proper mirroring)	S6	S7
(Need to adjust for proper mirroring)	S	= 2 S
	4	5

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