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Allen and Holberg - CMOS Analog Circuit Design

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Allen and Holberg - CMOS Analog Circuit Design

Page V.3-4

CASCODE CURRENT SINK

MOS

Circuit

Small-Signal Model

 

IREF

iOUT

 

 

iout

+

 

 

M4

M2

 

 

+

 

 

 

 

 

vOUT

gm2vgs2

 

r ds2

 

gmbs2vbs2

 

 

M3 M1

-

 

+

vout

 

 

 

 

 

r ds1

 

 

 

vS2

 

 

 

gm1vgs1

-

-

vout

vout

rout

Note : vMIN

=[iout - (gm2vgs2 + gmbs2vbs2)]rds2 + ioutrds1

=iout[rds2 + gm2rds2r(1 + η2) + rds1]

=rds2 + r[1 + gm2rds2(1 + η2)] rds1gm2rds2(1 + η2)

= VT + 2VON 0.75 + 1.5 = 2.25 (assuming VON ≈ VT)

NMOS Cascode-

1mA

 

 

 

 

 

Slope = 1/Ro

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.75mA

 

 

 

 

 

 

 

 

iO

 

 

 

 

 

 

 

+

 

+

iO 0.5mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

vGS2

 

 

 

 

 

 

 

 

 

-

 

vO

 

 

 

 

 

 

 

 

 

 

 

0.25mA

 

 

 

 

 

 

+

 

 

 

 

 

 

 

 

 

vGS1

 

 

 

 

 

 

 

 

 

-

 

 

 

 

 

 

VMIN

-

 

 

0mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2V

4V

 

6V

 

8V

10V

0V

 

 

 

 

 

 

vO

 

 

 

 

 

Allen and Holberg - CMOS Analog Circuit Design

Page V.3-5

Gate-Source Matching Principle

iD2

iD1

 

 

iD2

+

M2

 

 

vGS2

 

 

 

 

 

 

 

-

 

M1

+

+

M2

 

iD1

vGS1

vGS2

 

 

 

 

 

-

-

 

 

 

 

 

 

 

+

M1

 

 

S = W/L

 

vGS1

 

 

 

 

 

 

 

 

-

 

Assume that M1 and M2 are matched but may not have the same W/L ratios.

1). If vGS1 = vGS2, then iD1 = (S1/S2)iD2

a). vGS1 may be physically connected together , or b). vGS1 may be equal to vGS2 by some other means.

2). If iD1 = iD2, then

a). vGS1 = VT + S2/S1(vGS2 b). If S1 = S2 and VS1 ≈ VS2

vGS1 = vGS2

- VT) , or then

Strictly speaking, absolute matching requires that vDS be equal for two matched devices.

Allen and Holberg - CMOS Analog Circuit Design

Page V.3-6

Reduction of VMIN or VOUT(sat)

High-Swing Cascode

Method 1 for Reducing the Value of vOUT(sat)

IREF

2VT + 2VON

IOUT

IOUT

 

 

 

 

 

 

 

VOUT(sat)

 

M4

 

+

 

 

+

M2

 

 

 

 

 

 

 

VT + VON

VOUT

 

 

 

-

 

 

 

M1

+

 

 

M3

+

VT + VON

 

 

 

 

 

 

 

VT + VON

-

 

 

 

-

-

0 VT + 2VON

VOUT

 

 

 

Standard Cascode Sink :

Part of vG S

vGS = VON + VT = to achieve +drain current

 

Part of vG S

to

 

 

 

enhance the channel

vDS(sat) = vGS - VT = (VON + VT) - VT = VON

iD

ID

vGS

VT

VT+VON

Above is based on the Gate-Source matching principle.

Allen and Holberg - CMOS Analog Circuit Design

Page V.3-7

Circuit Which Reduces the Value of Vout(sat) of the Cascode Current Sink

iREF

iREF

iout

M6

1/4

M5

iOUT

vOUT(sat)

0 2VON

 

M4

 

 

+

+

+

1/1

1/1

 

 

M2

VT + 2VON

VT + VON

 

 

 

+

 

-

-

 

 

 

VT + VON

vOUT

2VT + 3VON

 

 

M3

 

-

 

 

VT + 2VON M1

+

 

 

 

 

 

+

1/1

 

VON

 

 

-

1/1

VT + VON

 

 

 

1/1

-

 

-

 

 

 

 

 

iD

W =

1

W = 1

 

L

1

L 4

ID

vOUT

0

V

vGS

 

VT + VON VT + 2VON

 

 

T

 

i

D

=

K'W

(v

GS

- V

) 2

=

K'W

(V

ON

) 2

 

 

2 L

 

T

 

 

2 L

 

 

Allen and Holberg - CMOS Analog Circuit Design

Page V.3-8

Method 2 for Reducing VMIN for MOS Cascode Sink/Source

i

iREF

 

REF

 

iO

 

 

 

 

M5

 

 

1

M4

 

 

 

 

 

 

 

 

 

 

+

 

 

 

1/4

V

T

+ V

ON-

 

M1

 

 

 

 

 

 

 

M2

+

 

 

 

 

 

 

 

+

 

 

 

 

VON

1

 

 

 

1

-

VT + VON

 

 

 

 

 

 

 

 

-

 

 

 

 

 

Assume (W/L)1 = (W/L)2 = (W/L)4 = 4(W/L)5 values are identical and ignore

bulk effects. Let IREF = IO

2IREF

VGS1 = W1 + VT = VON + VT K’ L1

and

2IREF

VGS5 = W5 + VT K’ L5

Since (W/L)1 = 4(W/L)5

VGS5

 

2IREF

 

 

=

W1

 

+ VT = 2

 

 

 

 

 

K’ 4L1

 

 

 

2IREF

W1 K’ L1

+ VT = 2 VON + VT

Allen and Holberg - CMOS Analog Circuit Design

Page V.3-9

Since VGS3 = VGS4 = VON +VT

VDS1 = VDS2 = VON

which gives a minimum output voltage while keeping all devices in saturation of v M I N = 2 V O N

Output Plot:

ID(M4)

1000 A

750 A

500 A

250 A

0 A

 

 

 

 

 

0V

1V

2V

3V

4V

5V

 

 

 

VOUT

 

 

Allen and Holberg - CMOS Analog Circuit Design

Page V.3-10

Matching Improved by Adding M3

iREF

+ M3

1

VT

- +

VT + VON

-

M1 +

VON

-1

iREF

iO

VT + 2VON

 

M5

1

 

 

M4

 

 

+

1/4

VT + VON

 

 

-

 

 

M2

 

 

+

+

 

VON

 

-

VT + VON

 

 

1

-

 

 

What is the purpose of M3?

The presence of M3 forces the VDS1 = VDS2 which is necessary to guarantee that M1 and M2 act alike (e.g., both will have the same VT).

Allen and Holberg - CMOS Analog Circuit Design

Page V.3-11

CMOS REGULATED CASCODE CURRENT SOURCE

Circuit Diagram

VDD

VDD

 

iOUT

iD3

 

 

 

 

 

 

IB2

RB2

 

 

 

 

 

M3

+

 

vGS3

 

 

 

 

 

IB1

 

 

 

 

 

 

M4

 

vOUT

Iout

 

 

 

 

 

M1

 

M2

 

 

 

 

 

 

 

 

 

 

 

-

VDS3(min)

vDS3

 

 

 

 

VDS3(sat)

Principle of operation:

As vOUT decreases, M3 will enter the non-saturation region and iOUT will begin to decrease. However, this causes a decrease in the gate-

source voltage of M4 which causes an increase in the gate voltage of M3. The minimum value of vOUT is determined by the gate-source voltage of

M4 and Vdsat of M3. Assume that all devices are in saturation.

vOUT(min) =

2IB2

 

2Iout

K'(W/L)4

+

+ VT4

 

 

K'(W/L)3

Allen and Holberg - CMOS Analog Circuit Design

Page V.3-12

CMOS REGULATED CASCODE CURRENT SOURCE - CONT.

Small Signal Model

 

 

 

r ds3

 

+

vgs3

-

 

iout

gm3vgs3

+

 

+

 

 

 

RB2 r ds4

vgs4

 

r ds2

vout

gm4vgs4

 

-

 

 

-

(Ignore bulk effects)

iout = gm3vgs3 + gds3(vout - vgs4)

vgs4 = ioutrds2

vgs3 = vg3 - vs3 = -gm4(rds4||RB2)vgs4 - vgs4

=-rds2[1 + gm4(rds4||RB2)]iout

iout = -gm3rds2[1 + gm4(rds4||RB2)]iout + gds3vout - gds3rds2iout

Solving for vout,

vout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||RB2)]iout

rout =

vout

+ gds3rds2 + gm3rds2gm4(rds4||RB2)]

= rds3[1 + gm3rds2

 

iout

 

 

 

 

 

g

m

2r3

 

rout = rds3gm3rds2gm4(rds4||RB2) =

 

 

2

Example

K'N = 25µA/V2, λ = 0.01, IB1 = IB2 = 100µA, all transistors with minimum geometry (W = 3µm, L=3µm), and RB2 = rds, we get

rds = 1MΩ and gm = 70.7µmho

rout≈ (1MΩ)(70.7µmho)((1MΩ)(70.7µmho)(1MΩ||1MΩ)= 2.5GΩ!!!

Allen and Holberg - CMOS Analog Circuit Design

Page V.3-13

CMOS REGULATED CASCODE CURRENT SOURCE - CONT.

SPICE Simulation

160 A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

140 A

 

 

 

 

 

 

 

 

 

 

I

 

 

=150 A

 

 

 

 

B1

 

 

120 A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

 

 

 

=125 A

 

100 A

 

 

 

 

B1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

=100 A

 

iOUT 80 A

 

 

 

 

B1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

 

=75 A

 

 

60 A

 

 

 

 

 

B1

 

 

 

 

 

 

 

 

 

 

 

 

 

40 A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

 

 

=50 A

 

 

 

 

 

 

 

 

 

 

B1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20 A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

2

3

 

 

 

4

 

 

5

vOUT

SPICE Input File

CMOS Regulated Cascode Current Sink VDD 6 0 DC 5.0

IB1 6 4 DC 25U VOUT 1 0 DC 5.0

M1 4 4 0 0 MNMOS1 W=15U L=3U

M2 3 4 0 0 MNMOS1 W=15U L=3U

M3 1 2 3 0 MNMOS1 W=30U L=3U

M4 2 3 0 0 MNMOS1 W=15U L=3U

M5 5 4 0 0 MNMOS1 W=15U L=3U

M6 5 5 6 6 MPMOS1 W=15U L=3U

M7 2 5 6 6 MPMOS1 W=6U L=3U

.MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6

.MODEL MPMOS1 PMOS VTO=-0.75 KP=8U +LAMBDA=0.02 GAMMA=0.4 PHI=0.6

.DC VOUT 5 0 0.1 IB1 50U 150U 25U

.OP

.PRINT DC ID(M3)

.PROBE

.END

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