Allen and Holberg - CMOS Analog Circuit Design
.pdfAllen and Holberg - CMOS Analog Circuit Design Page VI.4-7
PUSH-PULL SOURCE FOLLOWER
VDD
VTR |
M2 |
Iout |
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vIN |
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Vout |
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VSS |
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VDD |
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VGG6 |
M6 |
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M5 |
Iout |
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Allen and Holberg - CMOS Analog Circuit Design |
Page VI.5-1 |
VI.5 - SUMMARY
• Analog Amplifier Building Blocks
Inverters - Class A Push-Pull - Class AB or B
Cascode - Increased bandwidth
Differential - Common mode rejection, good input stage Output - Low output resistance with minimum distortion
Allen and Holberg - CMOS Analog Circuit Design |
Page VII.1-1 |
VII.1 - CHARACTERIZATION OF
COMPARATORS
What is a Comparator?
A comparator is a circuit which compares two analog signals and outputs a binary signal based on the comparsion. (It can be an op amp without frequency compensation.)
Characterization of Comparators
We shall characterize the comparator by the following aspects:
•Resolving capability
•Speed or propagation time delay
•Maximum signal swing limits
•Input offset voltage
•Other Considerations
Noise
Power
Etc.
Allen and Holberg - CMOS Analog Circuit Design |
Page VII.1-3 |
COMPARATOR PERFORMANCE
1. Speed or propagation time delay.
The amount of time between the time when VA - VB = 0 and the output is 50% between initial and final value.
2. Resolving capability.
The input change necessary to cause the output to make a transition between its two stable states.
3. Input common mode range.
The input voltage range over which the comparator can detect VA = VB.
4.Output voltage swing (typically binary).
5.Input offset voltage.
The value of VOUT reflected back to the input when VA is physically connected to VB.
Allen and Holberg - CMOS Analog Circuit Design |
Page VII.1-4 |
APPROACHES TO THE DESIGN OF VOLTAGE
COMPARATORS
Open Loop
Use of a high-gain differential amplifier.
VOH - VO L
Gain = resolution of the comparator
Regenerative
Use of positive feedback to detect small differences between two voltages, VA and VB. I.e., sense amplifiers in digital memories.
Open Loop - Regenerative
Use of low gain, high speed comparator cascaded with a latch. Results in comparators with very low propagation time delay.
Charge Balancing
Differential charging of a capacitor. Compatible with switched capacitor circuit techniques.
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Offset Voltage |
Resolution |
Speed (8 bit) |
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Open-loop |
1-10 mV |
300 V (±5V) |
10 MHz |
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Regenerative |
0.1 mV |
50 V (±5V) |
50 MHz |
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Charge |
0.1 mV |
5mV (5V) |
30 MHz |
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Balancing |
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Allen and Holberg - CMOS Analog Circuit Design |
Page VII.1-5 |
COMPARATOR MODELS - OPEN LOOP
Zero Order Model
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VP - VN |
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Model
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fo VP - VN |
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VN |
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V O H |
for ( V P - VN ) |
≥ 0 |
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fo( V P - VN ) = |
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for ( V P - VN ) |
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