Allen and Holberg - CMOS Analog Circuit Design
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Allen and Holberg - CMOS Analog Circuit Design |
Page VII.7-1 |
VII.7 - COMPARATOR SUMMARY
• Key performance parameters: Propagation time delay Resolving capability
Input common mode swing Input offset voltage
•Types of comparators: Open loop Regenerative
Open loop and regenerative Charge balancing
•Open loop comparator needs differential input and second stage
•Systemative offset error is offset (using perfectly matched transistors) that is due to current mirror errors.
•For fast comparators, keep all node swings at a minimum except for the output (current comparators?).
•Key design equations:
iD = |
KW |
(vGS-VT) 2, vDS(sat) = |
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, and gm = |
2KWID |
2L |
K(W/L) |
L |
•Positive feedback is used for regenerative comparators.
•Use autozeroing to remove offset voltages (charge injection is limit).
•Fastest comparators using low-gain, fast open loop amplifiers cascaded with a latch.
Allen and Holberg - CMOS Analog Circuit Design |
Page VII.0-1 |
VIII. SIMPLE CMOS OPERATIONAL AMPLIFIERS (OP AMPS) AND OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS (OTA'S)
Contents
VIII.1 |
Design Principles |
VIII.2 |
OTA Compensation |
VIII.3 |
Two-Stage CMOS OTA Design |
Organization |
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Chapter 10 |
Chapter 11 |
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D/A and A/D |
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Analog Systems |
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Converters |
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SYSTEMS |
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Chapter 7 |
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Chapter 8 |
Chapter 9 |
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CMOS |
Simple CMOS Op |
High Performance |
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Comparators |
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Amps |
OTA's |
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COMPLEX |
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CIRCUITS |
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Chapter 5 |
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Chapter 6 |
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CMOS |
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CMOS Amplifiers |
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Subcircuits |
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SIMPLE |
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Chapter 2 |
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Chapter 3 |
Chapter 4 Device |
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CMOS |
CMOS Device |
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Characterization |
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Technology |
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Modeling |
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DEVICES |
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Allen and Holberg - CMOS Analog Circuit Design
Frequency Response
Av(s) = |
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Av0 |
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s − 1 ) ( |
s − 1 ) ( |
s − 1 ) . . . |
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p1 |
p2 |
p3 |
Gain, dB
2
ω3
0 dB
ω1
Frequency
180
Phase (degrees)
90
Phase margin
0
Frequency
-90
Allen and Holberg - CMOS Analog Circuit Design
Power supply rejection ratio (PSRR):
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vout |
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VDD |
Avd(s) |
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vin |
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PSRR = |
· Avd(s) = |
Aps(s) |
vout |
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vOUT |
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(vin=0) |
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vps |
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Common-mode input range (ICMR).
Maximum common mode signal range over which the differential
voltage gain of the op amp remains constant.
Maximum and minimum output voltage swing.
Slew rate:
vOUT
Slew rate = max t
10V
5V 
Output Voltage
0V
-5V
Input 
Voltage
-10V |
2 s |
4 s |
6 s |
8 s |
10 s |
0 s |
Time
Allen and Holberg - CMOS Analog Circuit Design
Settling Time
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1.4 |
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1.2 |
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Upper tolerance |
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1 |
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Vout(t) |
0.8 |
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Lower tolerance |
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0.6 |
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Settling |
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0.4 |
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time |
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0.2 |
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0 |
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Time (sec) |
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Allen and Holberg - CMOS Analog Circuit Design
Design Approach
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Design |
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Specifications |
Iterate |
Analysis |
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Simulation |
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Modify |
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Specifications: |
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Gain |
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Bandwidth |
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Output voltage swing |
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PSRR |
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Settling time |
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CMRR |
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Power dissipation |
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Noise |
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Supply voltage |
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Common-mode input range |
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Silicon area |
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