Verilog

3.3. How to include memory elements using PLS prestored library

The instantiation of memory elements is made by prestored module instantiations. PLS provides predefined modules corresponding to single bit flip-flops and latches with or without asynchronous clear and preset inputs are described. The flip-flops are positive edge triggered and the latches are high level sensitive (transparent when the enable input is 1). These modules are located in the library "asyllib.v".

These modules are :

-DFF (DATA,CLOCK,Q) : D flip-flop,

-DFFC (DATA,CLEAR,CLOCK,Q) :

Dflip-flop with an active high asynchronous Clear,

-DFFP (DATA,PRESET,CLOCK,Q) :

Dflip-flop with an active high asynchronous Preset,

-DFFPC (DATA,PRESET,CLEAR,CLOCK,Q) :

Dflip-flop with active high asynchronous Clear and Preset,

-DLATCH (DATA,ENABLE,Q) :

DLatch,

-DLATCHC (DATA,CLEAR, ENABLE,Q) :

DLatch with an active high asynchronous Clear,

-DLATCHP (DATA,PRESET, ENABLE,Q) :

DLatch with an active high asynchronous Preset,

-DLATCHPC (DATA,PRESET, CLEAR, ENABLE,Q) :

DLatch with active high asynchronous Clear and Preset,

The full definition of these modules is available for in the file "asyllib.v". You must include this file in your Verilog desccription if you want to use one of these modules.

By default, all these memory elements are of size one but for vectored flip-flops and latches, it is possible to override the size of the module when it is instantiated. An example is given in figure 22. The synthesized netlist is shown in figure 23.

'include "asyllib.v"

module EXAMPLE ( DI, CLK, DO) ; input [7:0] DI ;

input CLK ; output [7:0] DO ;

DFF #(8) DFF ( DI, CLK, DO); endmodule

Figure 22: Example of sequential netlist

Verilog - 11

Verilog

Figure 23: Synthesized netlist

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