Verilog

5. General examples using all the Verilog styles

The following examples have been described to illustrate the structural, data flow and behavioral Verilog styles explained in this section.

5.1. Example 1: timer/counter (prepbenchmark 2)

Example 1 is an 8-bit timer/counter. It includes a loadable comparator and a multiplexor which allows the binary up-counter to be preloaded from either a latched value or a value available from a data bus. The block diagram is shown in figure 45.

Figure 52 gives the Verilog description of this example. It is a mixture of structural and data flow styles.

In the top level module named “PREP2” the register, counter and comparator blocks are declared as modules and their descriptions are given at the beginning of the Verilog file. The multiplexor is described in a data flow style using the “assign” statement. Figure 46 gives the top level Verilog description of the 8-bit timer/counter.

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Verilog

module TOP_LEVEL ( CLK, RST, SEL, LDCOMP, LDPRE, DATA1, DATA2, DATA0);

input CLK, RST, SEL, LDCOMP, LDPRE; input [7:0] DATA1, DATA2;

output [7:0] DATA0;

wire [7:0] QPRE, QCOMP, QX, YX; wire LD;

PREP2_REG ONE (CLK, RST, LDPRE, DATA2, QPRE); PREP2_REG TWO (CLK, RST, LDCOMP, DATA2,

QCOMP);

PREP2_COUNT THREE (CLK, RST, LD, YX, QX); PREP2_COMP FOUR (QX, QCOMP, LD);

assign YX = (SEL == 1'b0) ? DATA1 : QPRE; assign DATA0 = QX;

endmodule

Figure 46: The Verilog top level description of the 8-bit timer/counter

The module “PREP2_REG” describes the register used in this example. The block diagram is shown in figure 47.

RST

Figure 47: The register block diagram

This register has a clock input: CLK, an asynchronous reset input: RST and an enable input: LE which allows the transfer of the input data D[7:0] to the output data Q[7:0] when a clock rising edge occurs. The register is described as a simple register without enable command. Its input data is connected to the output data of a multiplexor. The command port of the multiplexor is connected to the enable port LE. The input data of the multiplexor is connected to the input data D[7:0] and output data Q[7:0] of the register. In the Verilog description, an internal signals: QX is declared. QX is used to connect the output data of the multiplexor to the input data of the simple register without enable.

Figure 48 gives the Verilog description of the register.

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Verilog

module PREP2_REG ( CLK, RST, LE, D, Q); input CLK, RST, LE;

input [7:0] D; ouput [7:0] Q; reg [7:0] Q; wire [7:0] QX;

assign QX = (LE == 1'b0) ? Q : D; always @(posedge CLK or posedge RST)

if (RST == 1’b1) Q = 8’b0 ;

else

Q = QX ; endmodule

Figure 48: The Verilog register description

The module “PREP2_COUNT” describes the counter. Figure 49 gives the block diagram.

RST

Figure 49: The counter block diagram

This counter has a clock input: CLK, an asynchronous reset input: RST and an enable input: LD which allows the transfer of the input data D[7:0] to the output data Q[7:0] when a clock rising edge occurs. If LD is low Q[7:0] is loaded with (Q[7:0] + 1). The incrementation is described using the Verilog operator “+”. 8'h01 is the notation used to express 1 in hexadecimal mode on 8 bits. Figure 50 gives the Verilog representation.

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Verilog

module PREP2_COUNT ( CLK, RST, LD, D, Q); input CLK, RST, LD;

input [7:0] D; output [7:0] Q; reg [7:0] Q ;

wire [7:0] QX, INCR;

assign QX = (LD == 1'b1) ? INCR : D; assign INCR = Q + 8'h01;

always @(posedge CLK or posedge RST) if (RST == 1’b1)

Q = 8’b0 ; else

Q = QX ; endmodule

Figure 50: The Verilog counter description

The module “PREP2_COMP” describes the comparator used in this example. This comparator has two inputs : A[7:0] and B[7:0] and one output: EQ which is equal to one if the inputs are equal. It is described in data flow style. Figure 51 gives the Verilog description.

module PREP2_COMP ( A, B, EQ); input [7:0] A, B;

output EQ;

assign EQ = (A == B); endmodule

Figure 51: The Verilog comparator description

The complete description is given below in figure 52.

module PREP2_REG ( CLK, RST, LE, D, Q); input CLK, RST, LE;

input [7:0] D; output [7:0] Q; reg [7:0] Q; wire [7:0] QX;

assign QX = (LE == 1'b0) ? Q : D; always @(posedge CLK or posedge RST)

if (RST == 1’b1) Q = 8’b0 ;

else

Q = QX ; endmodule

module PREP2_COUNT ( CLK, RST, LD, D, Q); input CLK, RST, LD;

input [7:0] D; output [7:0] Q; reg [7:0] Q;

wire [7:0] QX, INCR;

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