Verilog

8.3. Unsupported Verilog Language Constructs

This section describes the Verilog constructs which are unsupported by PLS.

8.3.1.Unsupported Definitions and Declarations

∙primitive definition.

∙macromodule definition.

∙time declaration.

∙event declaration.

∙triand, trior, tri0, tri1, and trireg net types.

8.3.2.Unsupported Statements

∙deassign statement.

∙defparam statement.

∙disable statement.

∙event control.

∙force statement.

∙release statement.

∙fork statement.

∙forever statement.

∙while statement.

8.3.3.Unsupported Operators

∙case equality and inequality operators (=== and !==).

∙division and modulus operators (/ and %) when the second operand is ot a power of two.

8.3.4.Unsupported Gate-Level constructs

∙nmos, pmos, rnmos and rpmos MOS Switches.

∙tran, tranif0, tranif1, rtran, rtranif0 and rtranif1 Bidirectional Pass Switches.

∙cmos and rcmos CMOS Gates.

∙pullup and pulldown Sources.

Verilog - 48