Verilog

8. Verilog Subset for synthesis

8.1. Limited Verilog Language Constructs

This section describes the Verilog constructs which are restricted by PLS.

8.1.1. always statement

PLS Verilog supports two kinds of always block, one using only edge-triggered events (a maximum of three) and the other using only value-change events.

8.1.2. for statement

PLS Verilog only supports for loop which are bounded by static variables.

8.1.3. repeat statement

PLS Verilog only supports repeat loop using a constant value.

8.2. Ignored Verilog Language Constructs

This section describes the Verilog constructs which are parsed and ignored by PLS.

8.2.1.Ignored Statements

∙specify statement.

∙initial statement.

∙system function call.

∙system task enable.

8.2.2.Ignored Miscellanous Constructs

∙delay specifications.

∙scalared and vectored declarations.

∙small, large and medium charge storage strengths.

∙weak0, weak1, highz0, highz1, pull0, pull1 driving strengths.

Verilog - 47