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Davis W.A.Radio frequency circuit design.2001

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40 IMPEDANCE MATCHING

circuit is shown in Fig. 3.4. In this circuit B1 and X2 both act as the impedance transforming elements while the third, B3 is the compensation element that tunes out the excess reactance from the first two elements. As in the L matching circuit, the first shunt element, B1, reduces the resistance level by a factor of 1/ 1 C Q12 , and X2 increases the resistance level by 1 C Q22 , where Q2 is a Q factor related to the second element. The final transformation ratio can be R00 < R or R00 > R depending on which Q is larger, as shown in the diagram of Fig. 3.5. To make R00 < R, make Q1 > Q2. The maximum Q, Qmax D Q1, will be the major factor that determines the bandwidth.

Now consider design of a circuit where R00 < R. Then the first shunt transformation gives

R0

D

R

 

3.30

1 C

Q2

 

 

1

 

X0

D R0Q1

3.31

The incremental reactance, X0, is added to the series arm. This results in the circuit shown in Fig. 3.6, where R has been transformed to R0 with a modified series reactance. This series reactance will act to increase the resistance level from R0 to R00. The second transformation Q is

Q

2

D

X2 R0Q1

D

R0 X2/R Q1

 

R0

R0

X 2

R "

 

 

B3

 

B1

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIGURE 3.4 impedance transformation circuit.

R "

R

 

 

 

 

 

 

 

 

1

1 + Q 2

 

 

 

 

 

 

 

 

 

 

 

 

 

1 + Q 2

 

2

 

 

 

 

 

 

1

 

 

 

R '

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIGURE 3.5 Diagram showing two-step transformation.

T TRANSFORMATION CIRCUIT

41

X '2 = X2 R 'Q1

R '

FIGURE 3.6 Equivalent series reactance after first transformation.

TABLE 3.2 p Matching Circuit Design Formulas

Step Number

R00 < R

R00 > R

1

Q1 D Qmax

Q2 D Qmax

2

R0 D R/ 1 C Q12

R0 D R00/ 1 C Q22

3

1 C Q22 D R00/R0

1 C Q12 D R/R0

4

X2 D R0 Q1 C Q2

X2 D R0 Q1 C Q2

5

B1 D Q1/R

B1 D Q1/R

6

B3 D Q2/R00

B3 D Q2/R00

or

 

 

X2

D Q1 C Q2

3.32

R0

The X2, B3 combination is a series L section with “load” of R0. Consequently

R00

D R0 1 C Q22

3.33

X00

D

R00

3.34

Q2

 

A summary for the design process is shown below. To make R00 < R, make Q1 > Q2 and Q1 D Qmax, and follow the design steps in the first column of Table 3.2. For R00 > R, use the second column.

3.7T TRANSFORMATION CIRCUIT

The T transformation circuit is the dual to the transformation circuit and is shown in Fig. 3.7. In this circuit, however, the series reactance X1 first raises the resistance level to R0, and the remaining shunt susceptance lowers the resistance level as indicated in Fig. 3.8. The design formulas are derived in the same way as the circuit formulas and are summarized in Table 3.3.

42

IMPEDANCE MATCHING

 

 

 

X3

 

X1

 

R"

B2

R

FIGURE 3.7 T transformation circuit.

R '

1 + Q 12

1

 

1 + Q 2

 

2

R

R "

FIGURE 3.8 Diagram showing impedance transformation for the T circuit.

TABLE 3.3 T Matching Circuit Design Formulas

Step Number

R00 > R

R00 < R

1

Q1 D Qmax

Q2 D Qmax

2

R0 D R 1 C Q12

R0 D R00 1 C Q22

3

1 C Q22 D R0/R00

1 C Q12 D R0/R

4

X1 D Q1R

X1 D Q1R

5

B2 D Q1 C Q2 /R0

B2 D Q1 C Q2 /R0

6

X3 D Q2/R00

X3 D Q2/R00

3.8TAPPED CAPACITOR TRANSFORMER

The tapped capacitor circuit is another approximate method for obtaining impedance level transformation. The description of this design process will begin with a parallel RC to series RC conversion. Then the tapped C circuit will be converted to an L-shaped matching circuit. The Q1 for an equivalent load resistance Reqv will be found. Finally, a summary of the circuit synthesis procedure will be given.

3.8.1Parallel to Series Conversion

Shown in Fig. 3.9 is a parallel RC circuit that will be forced to have the same impedance as the series RC circuit, at least at one frequency. The conversion is of

TAPPED CAPACITOR TRANSFORMER

43

R s

C p

R p

=

C s

FIGURE 3.9 Parallel RC to series RC conversion.

course valid for only a narrow frequency range, so this method is fundamentally limited by this approximation.

The impedance of the parallel circuit is

Rp

3.35

Zp D 1 C sCpRp

The Q for a parallel circuit is Qp D ωCpRp. The equivalent series resistance and reactance in terms of Qp are

Rseqv D

 

Rp

 

3.36

1 C Qp2

Xseqv D

XpQp2

3.37

1 C Qp2

3.8.2Conversion of Tapped C Circuit to an L-Shaped Circuit

The schematic of the tapped C circuit is shown in Fig. 3.10 where R0 is to be matched to R2. The parallel R2C2 section is converted to a series ReqvCeqv, as indicated in Fig. 3.11. Making use of Eqs. (3.36) and (3.37),

Cseqv D C2

 

1 C Qp2

for high Qp

 

 

 

³ C2

 

Qp2

Rseqv D R D

 

R2

 

 

 

1 C Qp2

 

 

where Qp D ω0C2R2. Considering R0 as the load, and using the L formation for a shunt circuit in Table 3.1,

R0

Rseqv D 1 C Q12

3.38

3.39

circuit trans-

3.40

44 IMPEDANCE MATCHING

C 1

R '

L

C 2

R 2

FIGURE 3.10 Tapped C transformation circuit.

 

C1

C seq v

R '

L

R = R seq v

FIGURE 3.11 Intermediate equivalent transformation circuit.

This is the transformed resistance looking through C1 toward the left. Looking toward the right through Cseqv and again using the parallel to series conversion, Eq. (3.36),

Rseqv D

R2

3.41

1 C Qp2

These two expressions for Rseqv can be equated and solved for Qp:

 

R2

1 C Q12 1

1/2

Qp D

3.42

R

3.8.3Calculation of Circuit Q

An approximate value for Q can be found by equating the impedances of the two circuits in Fig. 3.12:

Z

D

R0ω2L2 C jR02ωL

D

R0

C

jωL

eqv

3.43

R02 C ωL 2

 

eqv

 

 

If the Q of the right-hand circuit is approximately that of the left-hand circuit in Fig. 3.12, then

Q1 D

ω0Leqv

D

ω0R02L

D

R0

3.44

Reqv0

R0ω02L2

ω0L

 

 

 

PARALLEL DOUBLE-TUNED TRANSFORMER

45

 

 

C

 

L eq v

C

 

R '

L

Z

Q 1

R 'eq v

Z

 

FIGURE 3.12 Equate the leftand right-hand circuits.

TABLE 3.4 Tapped C Matching Circuit Design Formulas

Step Number

 

 

Tapped C Formula

 

 

 

 

 

 

 

1

Q1 D f0/ f

 

 

 

 

2

C

D

Q /ω

R0

D

1/2 fR0

 

 

 

1 2 0

 

 

 

 

3

L D 10C

 

1 C Q12

1

1/2

4

Qp D R2/R0

 

5

C2 D Qp0R2

2

2

 

6

Cseqv D C2 1 C Qp /Qp

 

7

C1 D CseqvC2/ Cseqv C2

 

The variable C represents the total capacitance of C1 and Cseqv in series, as implied in Fig. 3.11 and represented in Fig. 3.12. For a high Q circuit, circuit analysis gives the resonant frequency:

ω02

1

 

 

 

1

 

3.45

D

 

³

 

 

 

LC L2/R02

LC

As a result the approximate value for Q1 can be found:

 

 

Q1 D ω0R0C D

f0

 

 

3.46

 

f

 

 

Here f is the bandwidth in Hz and f0 is the resonant frequency.

3.8.4Tapped C Design Procedure

The above ideas are summarized in Table 3.4, which provides a design procedure for the tapped C matching circuit. Similar expressions could be found for a tapped inductor transforming circuit, but such a circuit is typically less useful because inductors are more difficult to obtain than capacitors.

3.9PARALLEL DOUBLE-TUNED TRANSFORMER

Each of the above described T, , or tapped C matching circuits provide some control over the bandwidth. Where precise control over the bandwidth is required, a double tuned circuit allows controlling bandwidth by specifying two different frequencies where maximum transmission occurs. For a small pass band, the

46 IMPEDANCE MATCHING

G T

f m1 f m2

FIGURE 3.13 Double tuned transformer response.

M

R G

C1

L11

L 22

C 2

RL

FIGURE 3.14 Real transformer with resonating capacitances.

midband dip in the transmission can be made small. Furthermore the double-tuned circuit is especially useful when a large difference in impedance levels is desired although its high end frequency range is limited. The filter transmission gain is shown in Fig. 3.13.

The double-tuned circuit consists of a coupled coil transformer with resonating capacitances on the primary and secondary side. This circuit is shown in Fig. 3.14. The transformer is described by its input and output inductance as well as the coupling coefficient k. The turns ratio for the transformer is

n : 1 D

L11

: 1

3.47

k2L22

The circuit in Fig. 3.14 can be replaced by an equivalent circuit using an ideal transformer (Fig. 3.15a). Since an ideal transformer has no inductance, the inductances and coupling factor, k, must be added to the ideal transformer. The final circuit topology is shown in Fig. 3.15b. Looking toward the right through the ideal transformer, Fig. 3.15b shows the circuit values are:

L20

 

1

 

1

3.48

D L11

 

 

 

k2

C20

D

 

L11

 

C2

3.49

 

k2L22

RL0

 

L11

 

3.50

D

 

RL

 

k2L22

 

 

 

PARALLEL DOUBLE-TUNED TRANSFORMER

47

 

 

n :1

L 22(1–k 2)

 

 

R G

C 1

L11

C 2

R L

 

(a )

L '2

R G

C 1

L 11

C '2

R 'L

(b )

FIGURE 3.15 (a) Alternate equivalent circuit with an ideal transformer, and (b) final equivalent circuit.

 

 

 

 

L '2

 

R G

C 1

L 11

R 2

C '2

R 'L

R 1

 

 

 

 

 

FIGURE 3.16 Double tuned circuit split into two.

The circuit elements will be chosen to give exact match at the two frequencies, fm1 and fm2. The circuit in Fig. 3.15b can be conceptually split into two (Fig. 3.16). The resistance R1 with the parallel resonant circuit will never be larger than RG. The right-hand side is an L matching circuit with the reactance of the shunt element monotonically decreasing with frequency. Hence R2 monotonically decreases. Consequently, if RL is small enough, there will be two frequencies where R1 D R2. This is illustrated in Fig. 3.17.

A design procedure for the parallel double-tuned circuit has been reviewed in [1] and is summarized below. The typical synthesis problem is to design a circuit that will match RG and RL over a bandwidth, f, at a center frequency, f0, with a given pass band ripple. The bandwidth and center frequency are approximated by the following:

1. Determine fm1 and fm2:

 

p

 

 

 

 

 

f ³

2 fm2 fm1

3.51

 

f0 ³

 

 

fm1fm2

 

3.52

48 IMPEDANCE MATCHING

Resistance

f m1

f m2

R 2

R 1

FIGURE 3.17 Plot of leftand right-hand resistance values versus frequency.

The minimum pass band gain for the filter is dependent on the difference between the match frequencies:

GTmin D

4fm2/fm1

3.53

fm2/fm1 2 C 2fm2/fm1 C 1

 

2. Determine the actual transducer gain for the given ripple factor:

 

GT D 10 ripple factor dB /10

3.54

3.Find the resistance ratio if GT > GTmin, the pass band ripple specification can be met:

 

 

r

D

1 C j1 GTj1/2

 

 

 

 

 

 

1 j1 GTj1/2

 

 

 

 

4.

Calculate the Q2 at the two matching frequencies:

 

 

 

 

Q22 m1 D r

fm1

 

1

 

 

 

 

 

 

fm2

 

 

 

 

 

 

Q22 m2 D r

fm2

 

1

 

 

 

 

 

 

fm1

 

 

 

 

5.

Solve the following simultaneous equations for L20

and C20 :

 

ωm1L20

C

1

 

D jQ2 m1j

 

 

 

RG

 

 

 

 

 

 

 

 

 

ω

C0

1

C

Q2

 

 

 

 

m1

2

 

 

 

 

 

 

2 m1

 

m2L20

C

1

 

D jQ2 m2j

 

 

 

RG

 

ωm2C20

1 C Q22 m2

 

6.

Find the value for RL0 :

 

 

 

 

1 C Q22 m1

 

 

 

 

 

 

 

 

 

R0

D

 

 

 

 

 

 

 

 

 

L

ωm2 1C202RG

 

 

 

 

 

 

3.55

3.56

3.57

3.58

3.59

3.60

PARALLEL DOUBLE-TUNED TRANSFORMER

49

7. Calculate the input susceptance of the right-hand side where G0L D 1/RL0 :

Bm1 D Im

 

1

 

 

m1L20

C 1/GL0

C jωm1C20

 

Bm2 D Im

 

1

 

 

 

 

 

 

m2L20

C 1/GL0

C jωm2C20

 

8. Solve the following simultaneous equations for L11 and C1:

1

ωm1C1 D jBm1j

ωm1L11

1

ωm2C1 D jBm2j

ωm2L11

9. Find the transformer coupling coefficient, and hence L22 and C2:

1

k D

1 C L20 /L11

L11RL

L22 D k2RL0

C2 D L11 C02

k2L22

3.61

3.62

3.63

3.64

3.65

3.66

3.67

This procedure has been coded into the program DBLTUNE, and an example of its use is given in Appendix C.

PROBLEMS

3.1Design an impedance transforming network that matches a generator resistance, RG D 400 " to a load resistance RL D 20 ". The center frequency for the circuit is f0 D 6 MHz. The desired ripple (where appropriate) is to be less than 0.25 dB. In some cases the ripple factor will not be able to be controlled in the design. The problem is to design four different transformation circuits with the specifications above, and for each design do an analysis using SPICE. See Appendix G, Sections G.1, and G.2.

(a)Design a two-element L matching circuit and check the results with SPICE.

(b)Design a three-element tapped capacitor matching circuit with a bandwidth f D 50 kHz, and check the results with SPICE to determine the actual bandwidth.

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