11 DMA Ports

Figure 11.1 ADSP-2181 System

11.2BDMA PORT

The ADSP-2181’s byte memory space is 8 bits wide and can address up to 4M bytes of program code or data. This memory space takes the place of the boot memory space found on other ADSP-2100 family processors. Unlike boot memory space, byte memory has read/write access through the ADSP-2181’s BDMA port.

Each read/write to byte memory consists of data (on data bus lines 15:8) and address (on address bus lines 13:0 plus data lines 23:16). The 22-bit byte memory address lets you access up to 4M bytes of ROM or RAM.

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Byte memory space consists of 256 pages, each containing 16K x 8-bit wide locations. This memory can be written and read in four different formats: 24-bit, 16-bit, 8-bit MSB alignment, and 8-bit LSB alignment.

To use byte memory for purposes other that boot loading, for example runtime access to bulk data storage, you must know the page (BMPAGE) that the code/data is stored on, the number of words (BWCOUNT) to read from that page, and the word format (BTYPE) of the data. Use the following procedure to prepare a runtime-accessible byte memory EPROM:

•Develop the data/code to be accessed at runtime

•Use the ADSP-2100 Family PROM Splitter utility to split the file into single page (or smaller) 16K x 8-bit-wide segments

•Program these pages into your EPROM, noting the offset (page number) of each

•Use these page numbers when doing BDMA accesses

Note: For more information on the ADSP-2100 Family Development Software Tools, see the ADSP-2100 Family Assembler Tools & Simulator Manual and current software release note.

When using BDMA for non-boot-loading transfers, a BDMA transfer begins when data is written to the BWCOUNT register and a BDMA interrupt is issued when the transfer is complete.

The following restrictions apply to BDMA transfers:

•The source or target of BDMA transfer is always internal program or data memory. The contents of the PMOVLAY and DMOVLAY registers do not influence BDMA source (or target selection).

•Do not access the BEAD or BIAD registers during BDMA transfers.

•Other external memory accesses (PM overlay, DM overlay, or I/O space) take precedence over BDMA port accesses. These accesses cannot occur at the same time because they also use the processor’s external bus.

•Do not enter powerdown mode with the BDMA port active. For information on powerdown restrictions on BDMA port access, see the System Interface chapter of this manual.

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11.2.1BDMA Port Functional Description

The BDMA Port lets you load (and store) program instructions and data from (and to) byte memory with very low processor overhead. While the ADSP-2181 is executing program instructions, the BDMA port reads (or writes) code or data from (or to) byte memory—stealing one ADSP-2181 cycle per word when it needs to write to (or read from) internal memory. You can calculate BDMA transfer time from the formula:

If, for example, you wanted to transfer 100 24-bit program memory words through the BDMA port, assuming five waitstates and no hold offs, the operation would take 1900 cycles. This is shown in the following equation:

Hold offs for DMA transfers are defined in the section “DMA Cycle Stealing, DMA Hold Offs, and IACKAcknowledge” at the end of this chapter.

11.2.2BDMA Control Registers

A set of memory-mapped registers are used to setup and control transfers through the BDMA port. Figures 11.2 through 11.6 show these registers.

The BDMA Internal Address Register (BIAD) lets you set the 14-bit internal memory starting address for a BDMA transfer. The BDMA External Address Register (BEAD) lets you set the 14-bit external memory starting address for a BDMA transfer.

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BDMA Internal Address

BIAD

Figure 11.2 BDMA Internal Address Register

BDMA External Address

BEAD

Figure 11.3 BDMA External Address Register

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11 DMA Ports

BDMA Control

Figure 11.4 BDMA Control Register

The BDMA Control Register lets you set:

•The BDMA Transfer Type (BTYPE)

•The BDMA Direction (BDIR)

•The BDMA Context Reset (BCR)

•The BDMA Page (BMPAGE)

BTYPE can be:

00 24-bit Program Memory Words

01 16-bit Data Memory

10 8-bit bytes for Data Memory, MSB alignment 10 8-bit bytes for Data Memory, LSB alignment

BDIR can be:

0from Byte Memory

1to Byte Memory

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BCR can be set to:

0Allow program execution during BDMA

1Inhibit program execution during BDMA transfers and cause a context reset after transfer is complete

BMPAGE lets you select the starting page for BDMA transfer.

Note: Rebooting with BDMA Context Reset (BCR=1) is similar to a Powerup Context Reset. For more details on processor states during reset and reboot, see the System Interface chapter of this manual.

The BWCOUNT register lets you start a BDMA transfer by writing the number of words for the transfer to this register. The count automatically decrements as the transfer proceeds. When the count is zero (i.e. transfer complete), the processor issues a BDMA interrupt. When MMAP and BMODE are set to zero on boot, a value of 32 (decimal) is written to this register directing the ADSP-2181 to load the first 32 locations of its internal program memory.

Two useful control techniques using this register are:

•Poll the BWCOUNT register to determine when the DMA transfer is complete (BWCOUNT=0), instead of waiting for the BDMA interrupt.

•Abort the DMA operation by writing a 1 to the BWCOUNT register and poll to determine when the transfer is complete (BWCOUNT=0), instead of waiting for the BDMA interrupt. (Note that the DMA transfer is aborted, and cannot be resumed later.)

BMWAIT consists of bits 12, 13, and 14 of the Programmable Flag & Composite Select Control Register. BMWAIT lets you select 0-7 waitstates (each equal to a single instruction cycle) to apply to each byte memory access. BMWAIT is set to 7 after a reboot.

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BDMA Word Count (MMAP=0 and BMODE=0)

BWCOUNT

or

BDMA Word Count (MMAP=1 or BMODE=1)

BWCOUNT

Figure 11.5 BDMA Word Count Register

Programmable Flag & Composite Select Control

Figure 11.6 BMWAIT Field (in Programmable Flag & Composite Select Control Register)

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