Instruction Set Reference 15

15.5ALU, MAC & SHIFTER INSTRUCTIONS

This group of instructions performs computations. All of these instructions can be executed conditionally except the ALU division instructions and the Shifter SHIFT IMMEDIATE instructions.

15.5.1ALU Group

Here is an example of one ALU instruction, Add/Add with Carry:

IF AC AR=AX0+AY0+C;

The (optional) conditional expression, IF AC, tests the ALU Carry bit (AC); if there is a carry from the previous instruction, this instruction executes, otherwise a NOP occurs and execution continues with the next instruction. The algebraic expression AR=AX0+AY0+C means that the ALU result register (AR) gets the value of the ALU X input and Y input registers plus the value of the carry-in bit.

Table 15.3 gives a summary list of all ALU instructions. In this list, condition stands for all the possible conditions that can be tested and xop and yop stand for the registers that can be specified as input for the ALU. The conditional clause is optional and is enclosed in square brackets to show this. A complete list of the permissible xops and yops is given in the reference page for each instruction. A complete list of conditions is given in Table 15.9.

ALU Instructions

–xop + C – 1

–xop + constant

–xop + constant + C – 1

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15 Instruction Set Reference

Table 15.3 ALU Instructions

15.5.2MAC Group

Here is an example of one of the MAC instructions, Multiply/Accumulate:

IF NOT MV MR=MR+MX0*MY0(UU);

The conditional expression, IF NOT MV, tests the MAC overflow bit. If the condition is not true, a NOP is executed. The expression MR=MR+MX0*MY0 is the multiply/accumulate operation: the multiplier result register (MR) gets the value of itself plus the product of the X and Y input registers selected. The modifier in parentheses (UU) treats the operands as unsigned. There can be only one such modifier selected from the available set. (SS) means both are signed, while (US) and (SU) mean that either the first or second operand is signed; (RND) means to round the (implicitly signed) result.

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Instruction Set Reference 15

Table 15.4 gives a summary list of all MAC instructions. In this list, condition stands for all the possible conditions that can be tested and xop and yop stand for the registers that can be specified as input for the MAC. A complete list of the permissible xops and yops is given in the reference page for each instruction.

MAC Instructions

Table 15.4 MAC Instructions

15.5.3Shifter Group

Here is an example of one of the Shifter instructions, Normalize:

IF NOT CE SR= SR OR NORM SI (HI);

The conditional expression, IF NOT CE, tests the “not counter expired” condition. If the condition is false, a NOP is executed. The destination of all shifting operations is the Shifter Result register, SR. (The destination of exponent detection instructions is SE or SB, as shown below.) In this example, SI, the Shifter Input register, is the operand. The amount and direction of the shift is controlled by the signed value in the SE register in all shift operations except an immediate shift. Positive values cause left shifts; negative values cause right shifts.

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