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Национальный исследовательский университет «МИЭТ»

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Документация по ЦСП Analog Devices / Appendix_E

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Control/Status Registers E

E.1 OVERVIEW

This appendix shows bit definitions for 1) the memory-mapped control registers and 2) other (non-memory-mapped) control and status registers of all ADSP-21xx processors. The memory-mapped registers are listed in descending address order. Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. Reserved bits are shown on a gray field. These bits should always be written with zeros.

Memory-Mapped Registers

System Control Register

15		14	13	12	11	10		9	8	7	6		5	4		3		2	1		0

	0	0	0	0	0		1	0	0	0		0	*		1		1	1		1		DM(0x3FFF)
	0	0	0	0	0		1	0	0	0		0	*		1		1	1		1		DM(0x3FFF)


SPORT0 Enable
1 = enabled, 0 = disabled
(set to 0 for ADSP-2105)																			PWAIT
																			PWAIT
SPORT1 Enable																			Program Memory
SPORT1 Enable																			Wait States
1 = enabled, 0 = disabled																			Wait States
1 = enabled, 0 = disabled
SPORT1 Configure															BWAIT
SPORT1 Configure															Boot Wait States*
1 = serial port															Boot Wait States*
1 = serial port															(not on ADSP-2181)
0 = FI, FO, IRQ0, IRQ1, SCLK															(not on ADSP-2181)
0 = FI, FO, IRQ0, IRQ1, SCLK
						BFORCE				BPAGE
				Boot Force Bit						Boot Page Select
			(not on ADSP-2181)							(not on ADSP-2181)

* Bit 5 initialized to 1 on ADSP-2171, ADSP-21msp58/59

Bit 5 initialized to 0 on ADSP-2101, ADSP-2105, ADSP-2115, ADSP-2111

E – 1

E Control/Status Registers

Processor Core

DATA ADDRESS GENERATORS

DAG1

DAG2

(DM addressing only)

(DM and PM addressing)

Bit-reverse capability

Indirect branch capability

PROGRAM SEQUENCER

LOOP

ICNTL

STACK

4 X 18

16 X 14

IFC*

OWRCNTR

SSTAT

CNTR

COUNT

IMASK*

MSTAT*

ASTAT

STACK

STATUS STACK*

4 X 14

* Width and depth vary with processor

ALU

MAC

AX0

AX1

AY0

AY1

MX0

MX1

MY0

MY1

MR2

MR1

MR0

SHIFTER

BUS EXCHANGE

SR1

SR0

TIMER

0x3FFD TPERIOD

0x3FFC TCOUNT

0x3FFB TSCALE

SPORT 0

RX0		TX0

Multichannel enables

0x3FFA	RX 31-16
0x3FF9	RX 15-0
0x3FF8	TX 31-16
0x3FF7	TX 15-0

SPORT0 Control

0x3FF6 Control

0x3FF5 SCLKDIV

0x3FF4 RFSDIV

0x3FF3 Autobuffer

SPORT 1

RX1 TX1

SPORT1 Control

0x3FF2 Control

0x3FF1 SCLKDIV

0x3FF0 RFSDIV

0x3FEF Autobuffer

MEMORY INTERFACE

	0x3FFF	System Control
	0x3FFF	Register
		Register

	0x3FFE	Wait States

	(ADSP-2181)
3	3

DMOVLAY PMOVLAY

ANALOG INTERFACE

(ADSP-21msp5x)


0x3FEF	Autobuffer

0x3FEE	Control

0x3FED	ADC Receive

0x3FEC	DAC Transmit

HOST INTERFACE PORT

IDMA PORT

BDMA PORT

(ADSP-2171, ADSP-2111, ADSP-21msp5x)

PROGRAMMABLE FLAGS

(ADSP-2181)

0x3FE8

Data Registers

HMASK

0x3FE5

IDMA Registers

BDMA Registers

HDR5

Status Registers

0x3FE0

IDMA Control

0x3FE4

BWCOUNT

0x3FE4

HDR4

0x3FE7

HSR7

0x3FE3

BDMA Control

HDR3

Programmable

0x3FE6

HSR6

0x3FE2

BEAD

0x3FE2

HDR2

Flag Registers

0x3FE1

BIAD

0x3FE1

HDR1

0x3FE6

PFTYPE

0x3FE0

HDR0

0x3FE5

PFDATA

E – 2

Control/Status Registers E

Memory-Mapped Registers

Waitstate Control Register

15		14		13		12		11	10		9	8	7		6	5	4		3	2	1	0

		1						1		1		1				1				1
	0	1			1		1	1		1	1	1		1	1	1		1	1	1	1	1	DM(0x3FFE)


			DWAIT4						DWAIT3				DWAIT2				DWAIT1			DWAIT0
					or					or				or				or			or
				DWAIT				IOWAIT3				IOWAIT2				IOWAIT1				IOWAIT0
		(ADSP-2181) (ADSP-2181)										(ADSP-2181)				(ADSP-2181)				(ADSP-2181)
					ROM Enable (ADSP-2172, ADSP-21msp59)
				1		= enable
				0		= disable

Timer Registers

15	14	13	12	11	10		9	8	7	6		5	4	3	2	1	0

						TPERIOD		Period			Register							DM(0x3FFD)


						TCOUNT		Counter			Register							DM(0x3FFC)
																		DM(0x3FFB)

0	0	0	0	0		0	0	0			TSCALE		Scaling		Register

	Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.	E – 3
	Reserved bits are shown on a gray field—these bits should always be written with zeros.	E – 3

E Control/Status Registers

Memory-Mapped Registers
				SPORT0 Control Register												(Not on ADSP-2105)
15		14	13	12	11	10	9	8	7	6	5	4	3	2		1	0

	0	0	0	0	0	0	0	0	0	0	0	0	0		0	0	0	DM(0x3FF6)

MCE
MCE
Multichannel Enable																	SLEN (Serial Word Length – 1)
ISCLK													DTYPE Data Format
Internal Serial Clock Generation													DTYPE Data Format
Internal Serial Clock Generation														00=right justify, zero-fill unused MSBs
RFSR														00=right justify, zero-fill unused MSBs
RFSR														01=right justify, sign-extend into unused MSBs
Receive Frame Sync Required														10=compand using -law

	RFSW	11=compand using A-law
	RFSW
	Receive Frame Sync Width	INVRFS
		INVRFS
	MFD	Invert Receive Frame Sync
	MFD
	Multichannel Frame Delay	INVTFS
	(Only If Multichannel Mode Enabled )	INVTFS
	(Only If Multichannel Mode Enabled )	Invert Transmit Frame Sync
		Invert Transmit Frame Sync
	TFSR	(or INVTDV Invert Transmit Data Valid)
	TFSR	(Only If Multichannel Mode Enabled )
	Transmit Frame Sync Required	(Only If Multichannel Mode Enabled )
	Transmit Frame Sync Required

IRFS

TFSW Internal Receive Frame Sync Enable

Transmit Frame Sync Width

ITFS

Internal Transmit Frame Sync Enable

(or MCL Multichannel Length:

1=32 words, 0=24 words)

(Only If Multichannel Mode Enabled )

			SPORT0 Multichannel Word Enables													(Not on ADSP-2105)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
																	DM(0x3FFA)
																	DM(0x3FFA)
Receive
Receive
Word	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Enables	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
																	DM(0x3FF9)



	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Transmit																	DM(0x3FF8)
																	DM(0x3FF8)

Word	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Enables	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Enables																	DM(0x3FF7)
																	DM(0x3FF7)
E – 4
E – 4						1 = channel enabled
						0 = channel ignored

Control/Status Registers E

Memory-Mapped Registers

			SPORT0 Autobuffer Control Register														(Not on ADSP-2105)
15	14		13	12	11	10	9	8		7	6	5	4	3	2	1	0

0		0	0	0												0	0	DM(0x3FF3)




																		RBUF

						TIREG			TMREG			RIREG		RMREG
						TIREG			TMREG			RIREG		RMREG				Receive Autobuffering Enable
																		Receive Autobuffering Enable

TBUF

Transmit Autobuffering Enable

BIASRND

MAC Biased Rounding Control Bit

(ADSP-2171, ADSP-2181, ADSP-21msp58/59 only)

CLKODIS

CLKOUT Disable Control Bit

(ADSP-2171, ADSP-2181, ADSP-21msp58/59 only)

						SPORT0 SCLKDIV									(Not on ADSP-2105)
				Serial Clock Divide Modulus											(Not on ADSP-2105)
				Serial Clock Divide Modulus
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

DM(0x3FF5)

SPORT0 RFSDIV

Receive Frame Sync Divide Modulus

DM(0x3FF4)

SCLKDIV =	CLKOUT frequency	– 1	RFSDIV =	SCLK frequency	– 1

	2 * (SCLK frequency)			RFS frequency

	Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.	E – 5
	Reserved bits are shown on a gray field—these bits should always be written with zeros.	E – 5

E Control/Status Registers

Memory-Mapped Registers

SPORT1 Control Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	DM(0x3FF2)

Flag Out (read-only)

SLEN (Serial Word Length – 1)

ISCLK

Internal Serial Clock Generation

RFSR

Receive Frame Sync Required

RFSW

Receive Frame Sync Width

TFSR

Transmit Frame Sync Required

TFSW

Transmit Frame Sync Width

ITFS

Internal Transmit Frame Sync Enable

DTYPE Data Format

00=right justify, zero-fill unused MSBs 01=right justify, sign-extend into unused MSBs 10=compand using -law

11=compand using A-law

INVRFS

Invert Receive Frame Sync

INVTFS

Invert Transmit Frame Sync

IRFS

Internal Receive Frame Sync Enable

SPORT1 SCLKDIV

Serial Clock Divide Modulus

DM(0x3FF1)

SPORT1 RFSDIV

Receive Frame Sync Divide Modulus

DM(0x3FF0)

SCLKDIV =	CLKOUT frequency	– 1	RFSDIV =	SCLK frequency	– 1
2 * (SCLK frequency)				RFS frequency

E – 6

Control/Status Registers E

Memory-Mapped Registers

		SPORT1 Autobuffer Control Register													(Not on ADSP-21msp5x)
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

0	0	0	0											0	0	DM(0x3FEF)
0	0	0	0											0	0	DM(0x3FEF)

XTALDIS

XTAL Pin Disable During Powerdown 1=disabled, 0=enabled (XTAL pin should be disabled when

no external crystal is connected)

XTALDELAY

Delay Startup From Powerdown 4096 Cycles 1=delay, 0=no delay (use delay to allow internal phase locked

loop or external oscillator to stabilize)

PDFORCE

Powerdown Force 1=force processor to vector to powerdown interrupt

PUCR

RBUF

Receive Autobuffer Enable

TBUF

Transmit Autobuffer Enable

RMREG

Receive M register

RIREG

Receive I register

TMREG

Transmit M register

TIREG

Transmit I register

Powerup Context Reset 1=soft reset (clear context)

0=resume execution XTALDIS, XTALDELAY, PDFORCE, and PUCR are only on the ADSP-2171, ADSP-2181, and ADSP-21msp58/59 processors.

		Analog Autobuffer Control Register													(ADSP-21msp5x only)
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

0 0 0 0

XTALDIS

XTAL Pin Disable During Powerdown 1=disabled, 0=enabled (XTAL pin should be disabled when

no external crystal is connected)

XTALDELAY

Delay Startup From Powerdown 4096 Cycles 1=delay, 0=no delay

0 0 DM(0x3FEF)

ARBUF

ADC Receive Autobuffer Enable

ATBUF

DAC Transmit Autobuffer Enable

ARMREG

Receive M register

ARIREG

Receive I register

PDFORCE	ATMREG
Powerdown Force	Transmit M register
1=force processor to vector to	ATIREG
powerdown interrupt	ATIREG
PUCR	Transmit I register
PUCR
Powerup Context Reset
1=soft reset, 0=resume execution

	Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.	E – 7
	Reserved bits are shown on a gray field—these bits should always be written with zeros.	E – 7

E		Control/Status Registers
Memory-Mapped Registers
						Analog Control Register												(ADSP-21msp5x only)
15		14	13	12	11	10		9	8	7	6	5	4	3	2	1	0

	0	0	0	0	0		0	0	0	0	0	0	0	0	0	0	0		DM(0x3FEE)

ADC Offset

IG0

ADC Input Gain (ADC PGA)

DABY

DAC High Pass Filter Bypass 1=bypass, 0=insert

ADBY

ADC High Pass Filter Bypass 1=bypass, 0=insert

IG1, IG0

ADC Input Gain (ADC PGA)

Gain	IG1	IG0
0 dB	0	0
+6 dB	0	1
+20 dB	1	0
+26 dB	1	1

OG2 OG1 OG0

				IG1
				ADC Input Gain (ADC PGA)
				IMS
				ADC Input Multiplexer Select
				1=AUX input, 0=NORM input
				OG2, OG1, OG0
				DAC Output Gain (DAC PGA)
				APWD
				Analog Interface Powerdown
				0=powerdown, 1=enable
OG2, OG1, OG0				(Set both bits to 1 to
OG2, OG1, OG0				enable analog interface)
DAC Output Gain (DAC PGA)

Gain	OG2	OG1	OG0
+6 dB	0	0	0
+3 dB	0	0	1
0 dB	0	1	0
–3 dB	0	1	1
–6 dB	1	0	0
–9 dB	1	0	1
–12 dB	1	1	0
–15 dB	1	1	1

					Analog Data Registers										(ADSP-21msp5x only)
					ADC Receive Data
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
																DM(0x3FED)

					DAC Transmit Data
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

DM(0x3FEC)

E – 8

Control/Status Registers E

Memory-Mapped Registers
					HMASK Interrupt Mask Register																			(ADSP-2171, ADSP-2111,
																								ADSP-21msp5x only)
15		14	13	12		11	10		9		8		7	6	5		4		3		2	1		0
																										DM(0x3FE8)
	0	0	0		0	0		0		0		0	0	0		0		0		0	0		0		0	DM(0x3FE8)
																										Host HDR0 Write
																										Host HDR0 Write
																										Host HDR1 Write
Host HDR5 Read																										Host HDR2 Write
Host HDR4 Read																										Host HDR3 Write
Host HDR3 Read																										Host HDR4 Write
Host HDR2 Read																										Host HDR5 Write
Host HDR1 Read
Host HDR0 Read

					HSR7 Status Register										(ADSP-2171, ADSP-2111,
															ADSP-21msp5x only)
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
																	DM(0x3FE7)
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0		0	DM(0x3FE7)

		21xx HDR0 Write
		21xx HDR1 Write
		21xx HDR2 Write
	OVERWRITE	21xx HDR3 Write
	MODE	21xx HDR3 Write
	MODE	21xx HDR4 Write
		21xx HDR4 Write
	SOFTWARE	21xx HDR5 Write
	RESET	21xx HDR5 Write
	RESET

	Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.	E – 9
	Reserved bits are shown on a gray field—these bits should always be written with zeros.	E – 9

E Control/Status Registers

Memory-Mapped Registers

							HSR6 Status Register												(ADSP-2171, ADSP-2111,
																			ADSP-21msp5x only)
15		14		13	12	11	10		9		8	7	6	5	4	3	2	1	0
																				DM(0x3FE6)
	0		0	0	0	0		0	0		0	0	0	0	0	0	0	0	0	DM(0x3FE6)
																				Host HDR0 Write
																				Host HDR0 Write
																				Host HDR1 Write
21xx HDR5 Write																				Host HDR2 Write
21xx HDR4 Write																				Host HDR3 Write
21xx HDR3 Write																				Host HDR4 Write
21xx HDR2 Write																				Host HDR5 Write
21xx HDR1 Write
21xx HDR0 Write
							HIP Data Registers											(ADSP-2171, ADSP-2111,
																		ADSP-21msp5x only)
										HDR5
		15	14	13	12	11	10		9	8	7	6	5	4	3	2	1	0
																			DM(0x3FE5)

										HDR4
		15	14	13	12	11	10		9	8	7	6	5	4	3	2	1	0
																			DM(0x3FE4)

										HDR3
		15	14	13	12	11	10		9	8	7	6	5	4	3	2	1	0
																			DM(0x3FE3)

										HDR2
		15	14	13	12	11	10		9	8	7	6	5	4	3	2	1	0
																			DM(0x3FE2)

										HDR1
		15	14	13	12	11	10		9	8	7	6	5	4	3	2	1	0
																			DM(0x3FE1)

										HDR0
		15	14	13	12	11	10		9	8	7	6	5	4	3	2	1	0

E – 10

DM(0x3FE0)

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