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Национальный исследовательский университет «МИЭТ»

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Программирование цифровых сигнальных процессоров

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Документация по ЦСП Analog Devices / Appendix_E

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<<< < Предыдущая 12 / 22

Control/Status Registers E

Memory-Mapped Registers

		Programmable Flag & Composite Select Control																				(ADSP-2181 only)
15	14		13		12	11		10	9	8		7		6	5	4	3	2		1	0

0		1		1			1	0	1		1		0		0		0		0	0		0
0		1		1	1		1	0	1		1		0	0	0	0	0		0	0		0	DM(0x3FE6)
							IOM	BM	DM		PM												DM(0x3FE6)

BMWAIT

CMSSEL

1 = Enable CMS

0 = Disable CMS

PFTYPE

1 = Output

0 = Input

					Programmable Flag Data										(ADSP-2181 only)
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

DM(0x3FE5)

PFDATA

E – 11

Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written with zeros.

E Control/Status Registers

Memory-Mapped Registers

							BDMA Control									(ADSP-2181 only)
15		14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

		0	0	0	0	0	0	0	0	0	0	0	1	0	0	0
	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	DM(0x3FE3)

					BTYPE (see table)
BMPAGE
					BDIR
					0 = load from BM
					1 = store to BM
BTYPE	00	01	10	11	1 = store to BM
BTYPE	00	01	10	11	BCR
Internal Memory Space		PM	DM	DM DM	BCR
Internal Memory Space		PM	DM	DM DM	0 = run during BDMA
Word Size	24	16	8	8	0 = run during BDMA
Word Size	24	16	8	8	1 = halt during BDMA,
Alignment	full	full	MSB LSB		1 = halt during BDMA,
Alignment	full	full	MSB LSB		context reset when done
	word	word

							BDMA Word Count											(ADSP-2181 only)
						(MMAP=0 and BMODE=0)
15	14	13		12	11	10		9	8	7	6	5	4	3	2	1	0

0	0		0		0		0	0	0	0	0	1	0	0	0	0	0
0	0		0	0	0		0	0	0	0	0	1	0	0	0	0	0		DM(0x3FE4)
																			DM(0x3FE4)

or														BWCOUNT
or
						BDMA Word Count
						(MMAP=1 or BMODE=1)
15		14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0
	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	DM(0x3FE4)
																	DM(0x3FE4)

BWCOUNT

E – 12

Control/Status Registers E

Memory-Mapped Registers

							BDMA External Address															(ADSP-2181 only)
15	14	13		12	11	10		9	8	7	6		5	4	3	2		1		0

0	0		0		0		0		0	0		0	0	0	0		0		0		0
0	0		0	0	0		0	0	0	0		0	0	0	0		0		0		0		DM(0x3FE2)
																							DM(0x3FE2)

BEAD

							BDMA Internal Address																(ADSP-2181 only)
15		14	13		12	11	10	9	8	7		6		5	4		3	2		1	0

	0	0		0		0	0		0		0		0	0		0	0		0	0		0
	0	0		0	0	0	0	0	0		0		0	0		0	0		0	0		0		DM(0x3FE1)
																								DM(0x3FE1)

BIAD

						IDMA Control									(ADSP-2181 only)
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

DM(0x3FE0)

	IDMAD
	Destination memory type	IDMAA
	0=PM, 1=DM	IDMAA
	0=PM, 1=DM	Starting address
		Starting address

E – 13

Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written with zeros.

E Control/Status Registers

Non-Memory-Mapped Registers

			ASTAT									SSTAT (read-only)
7	6	5	4		3	2	1	0	7	6	5	4		3	2	1	0

0	0	0		0	0	0	0	0	0	1	0		1	0	1	0	1

SS	MV	AQ		AS	AC	AV	AN	AZ

PC Stack Empty

ALU Result Zero

PC Stack Overflow

ALU Result Negative

Count Stack Empty

ALU Overflow

Count Stack Overflow

ALU Carry

Status Stack Empty

ALU X Input Sign

Status Stack Overflow

ALU Quotient

Loop Stack Empty

MAC Overflow

Loop Stack Overflow

Shifter Input Sign

		MSTAT							ICNTL
6	5	4	3	2	1	0		4	3	2	1	0

0	0	0	0	0	0	0
							Register Bank Select
							Register Bank Select
							0=primary, 1=secondary
							Bit-Reverse Addressing Enable (DAG1)
							ALU Overflow Latch Mode Enable						IRQ0 Sensitivity	1=edge
							ALU Overflow Latch Mode Enable						IRQ1 Sensitivity

							AR Saturation Mode Enable							0=level
													IRQ2 Sensitivity	0=level


							MAC Result Placement
							0=fractional, 1=integer						Interrupt Nesting
							Timer Enable						1=enable
													0=disable

Go Mode Enable

E – 14

Control/Status Registers E

Non-Memory-Mapped Registers

		IMASK					ADSP-2101
		IMASK					ADSP-2105
5	4	3	2	1	0		ADSP-2115
						INTERRUPT ENABLES
0	0	0	0	0	0	INTERRUPT ENABLES
0	0	0	0	0	0	1	= enable
						1	= enable
						0	= disable (mask)
						0	= disable (mask)

Timer

SPORT1 Receive or IRQ0

SPORT1 Transmit or IRQ1

SPORT0 Receive (must be set to 0 for ADSP-2105)

SPORT0 Transmit (must be set to 0 for ADSP-2105)

IRQ2

IFC (write-only)

11	10	9	8	7	6	5	4	3	2	1	0

0	0	0	0	0	0	0	0	0	0	0	0

INTERRUPT FORCE BITS

IRQ2

SPORT0 Transmit

(must be set to 0 for ADSP-2105)

SPORT0 Receive

(must be set to 0 for ADSP-2105)

SPORT1 Transmit or IRQ1

SPORT1 Receive or IRQ0

Timer

ADSP-2101

ADSP-2105

ADSP-2115

ADSP-2111

INTERRUPT CLEAR BITS

Timer

SPORT1 Receive or IRQ0

SPORT1 Transmit or IRQ1

SPORT0 Receive

(must be set to 0 for ADSP-2105)

SPORT0 Transmit

(must be set to 0 for ADSP-2105)

IRQ2

	Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.	E – 15
	Reserved bits are shown on a gray field—these bits should always be written with zeros.	E – 15

E Control/Status Registers

Non-Memory-Mapped Registers

			IMASK						ADSP-2111
7	6	5	4	3	2	1	0	INTERRUPT ENABLES

0	0	0	0	0	0	0	0
0	0	0	0	0	0	0	0	1	= enable
								1	= enable
								0	= disable (mask)
								0	= disable (mask)

	Timer
	SPORT1 Receive or IRQ0
IRQ2	SPORT1 Transmit or IRQ1
HIP Write	SPORT0 Receive
HIP Read	SPORT0 Transmit

E – 16

Control/Status Registers E

Non-Memory-Mapped Registers

				IMASK							ADSP-2181
9	8	7	6	5	4	3	2	1	0	INTERRUPT ENABLES

0	0	0	0	0	0	0	0	0	0
0	0	0	0	0	0	0	0	0	0	1	= enable
										0	= disable (mask)

IRQ2	Timer
IRQL1	SPORT1 Receive or IRQ0
IRQL0	SPORT1 Transmit or IRQ1
SPORT0 Transmit	BDMA Interrupt
SPORT0 Receive	IRQE

								IFC (write-only)									ADSP-2181
15		14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
																	INTERRUPT CLEAR BITS
INTERRUPT FORCE BITS
INTERRUPT FORCE BITS
IRQ2																	Timer
SPORT0 Transmit																	SPORT1 Receive or IRQ0
SPORT0 Receive																	SPORT1 Transmit or IRQ1
IRQE																	BDMA Interrupt
BDMA Interrupt																	IRQE
SPORT1 Transmit or IRQ1																	SPORT0 Receive
SPORT1 Receive or IRQ0																	SPORT0 Transmit
Timer																	IRQ2

	Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.	E – 17
	Reserved bits are shown on a gray field—these bits should always be written with zeros.	E – 17

E Control/Status Registers

Non-Memory-Mapped Registers

				IMASK							ADSP-2171
9	8	7	6	5	4	3	2	1	0	INTERRUPT ENABLES

0	0	0	0	0	0	0	0	0	0
0	0	0	0	0	0	0	0	0	0	1	= enable
										0	= disable (mask)

IRQ2	Timer
HIP Write	SPORT1 Receive or IRQ0
HIP Read	SPORT1 Transmit or IRQ1
SPORT0 Transmit	Software Interrupt 0
SPORT0 Receive	Software Interrupt 1

								IFC (write-only)									ADSP-2171
15		14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
																	INTERRUPT CLEAR BITS
INTERRUPT FORCE BITS																	INTERRUPT CLEAR BITS
IRQ2																	Timer
SPORT0 Transmit																	SPORT1 Receive or IRQ0
SPORT0 Receive																	SPORT1 Transmit or IRQ1
Software Interrupt 1																	Software Interrupt 0
Software Interrupt 0																	Software Interrupt 1
SPORT1 Transmit or IRQ1																	SPORT0 Receive
SPORT1 Receive or IRQ0																	SPORT0 Transmit
Timer																	IRQ2

E – 18

Control/Status Registers E

Non-Memory-Mapped Registers

				IMASK							ADSP-21msp5x
9	8	7	6	5	4	3	2	1	0	INTERRUPT ENABLES

0	0	0	0	0	0	0	0	0	0
0	0	0	0	0	0	0	0	0	0	1	= enable
										0	= disable (mask)

IRQ2	Timer
HIP Write	SPORT1 Receive or IRQ0
HIP Read	SPORT1 Transmit or IRQ1
SPORT0 Transmit	ADC Receive
SPORT0 Receive	DAC Transmit

								IFC (write-only)									ADSP-21msp5x
15		14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
																	INTERRUPT CLEAR BITS
INTERRUPT FORCE BITS
INTERRUPT FORCE BITS
IRQ2																	Timer
SPORT0 Transmit																	SPORT1 Receive or IRQ0
SPORT0 Receive																	SPORT1 Transmit or IRQ1
DAC Transmit																	ADC Receive
DAC Transmit																	DAC Transmit
ADC Receive																	DAC Transmit
ADC Receive																	SPORT0 Receive
SPORT1 Transmit or IRQ1																	SPORT0 Receive
SPORT1 Transmit or IRQ1																	SPORT0 Transmit
SPORT1 Receive or IRQ0																	SPORT0 Transmit
SPORT1 Receive or IRQ0
Timer																	IRQ2

	Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.	E – 19
	Reserved bits are shown on a gray field—these bits should always be written with zeros.	E – 19

E Control/Status Registers

Processor Core

DATA ADDRESS GENERATORS

DAG1

DAG2

(DM addressing only)

(DM and PM addressing)

Bit-reverse capability

Indirect branch capability

PROGRAM SEQUENCER

LOOP

ICNTL

STACK

4 X 18

16 X 14

IFC*

OWRCNTR

SSTAT

CNTR

COUNT

IMASK*

MSTAT*

ASTAT

STACK

STATUS STACK*

4 X 14

* Width and depth vary with processor

ALU

MAC

AX0

AX1

AY0

AY1

MX0

MX1

MY0

MY1

MR2

MR1

MR0

SHIFTER

BUS EXCHANGE

SR1

SR0

TIMER

0x3FFD TPERIOD

0x3FFC TCOUNT

0x3FFB TSCALE

SPORT 0

RX0		TX0

Multichannel enables

0x3FFA	RX 31-16
0x3FF9	RX 15-0
0x3FF8	TX 31-16
0x3FF7	TX 15-0

SPORT0 Control

0x3FF6 Control

0x3FF5 SCLKDIV

0x3FF4 RFSDIV

0x3FF3 Autobuffer

SPORT 1

RX1 TX1

SPORT1 Control

0x3FF2 Control

0x3FF1 SCLKDIV

0x3FF0 RFSDIV

0x3FEF Autobuffer

MEMORY INTERFACE

	0x3FFF	System Control
	0x3FFF	Register
		Register

	0x3FFE	Wait States

	(ADSP-2181)
3	3

DMOVLAY PMOVLAY

ANALOG INTERFACE

(ADSP-21msp5x)


0x3FEF	Autobuffer

0x3FEE	Control

0x3FED	ADC Receive

0x3FEC	DAC Transmit

HOST INTERFACE PORT

IDMA PORT

BDMA PORT

(ADSP-2171, ADSP-2111, ADSP-21msp5x)

PROGRAMMABLE FLAGS

(ADSP-2181)

0x3FE8

Data Registers

HMASK

0x3FE5

IDMA Registers

BDMA Registers

HDR5

Status Registers

0x3FE0

IDMA Control

0x3FE4

BWCOUNT

0x3FE4

HDR4

0x3FE7

HSR7

0x3FE3

BDMA Control

HDR3

Programmable

0x3FE6

HSR6

0x3FE2

BEAD

0x3FE2

HDR2

Flag Registers

0x3FE1

BIAD

0x3FE1

HDR1

0x3FE6

PFTYPE

0x3FE0

HDR0

0x3FE5

PFDATA

E – 20

<<< < Предыдущая 12 / 22

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