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TMS320C64x™ DSP Generation, Fixed Point

Highest Performance DSPs

Specifications

•TMS320C64x DSP high performance core provides scalable performance of up to 1.1 GHz

•The industry’s fastest DSPs with up to 600 MHz (4800 MIPS) performance

•C64x DSPs are software compatible with TI’s C62x™ DSPs

Applications

DSL and pooled modems, basestation transceivers, wireless LAN, enterprise PBX, multimedia gateway, broadband video transcoders, streaming video servers and clients, highspeed raster image processing (RIP) engines, network cameras

Features

•300- (C6411 only), 500-, and

600-MHz (C6414, C6415, C6416, DM642 only) options enable 2400, 4000, and 4800 MIPS respectively

TMS320C6411 DSP – Low-cost C64x DSP performance

•250 mW power dissipation

•256 KBytes L2 memory

TMS320C6414 DSP – Setting the industry’s performance standard

•Three multi-channel buffered serial ports (McBSPs)

•32-bit host port interface (HPI)

TMS320C6415 DSP – Adds industry standard interfaces for multimedia and media gateway systems

•Flexible 32-bit/33-MHz PCI or 32-bit HPI

•Flexible universal test and operations PHY interface for ATM (UTOPIA) or McBSP

TMS320C6416 DSP – Customized for 3G wireless infrastructure

•Viterbi decoder co-processor (VCP) supports over 350 voice channels at 12.2 kbps

•Turbo decoder co-processor (TCP) supports 35 data channels at 384 kbps

TMS320DM642 DSP – Provides a rich peripheral set for multimedia client systems

•Flexible audio and BT656 video ports

•Flexible 32-bit/66-MHz PCI or 32-bit HPI or Ethernet MAC

TMS320C6000™ DSP Platform Roadmap

	Software Compatible
	Roadmap
	In Development
	In Silicon				Multicore		Floating
					Multicore
						C64x DSP Pt
						1.1 GHz
Performance			Second Generation			3G Wireless
					C64x™ DSP	3G Wireless
			General		C64x™ DSP	Infrastructure
			General	C6414	C6415	C6416	DM642
			Purpose	C6414	C6415	C6416	DM642
					Media	C6411	Video
First Generation					Gateway		Client
First Generation
	C6203		C6713
	C6203
C6201	C6202	C6204	C62x™
	C6211	C6204	C6205	DSP
	C6211		C6205	DSP
	C6701	C6711	C6712	C67x™
		C6711	C6712	DSP
				DSP
					Time

The TMS320C6000 DSP platform includes a wide range of devices that raise the bar in performance, set new levels of cost efficiency and offer low power dissipation enabling developers of highperformance systems to choose the device that best suits their specific application.

See page 32 for the TI Floating-Point DSP roadmap.

TMS320C6411/C6414/C6415/C6416 DSP Block Diagram

Timer 0	VCP†	†The VCP and TCP processors exist only on the C6416 DSP.
	(C6416 DSP only)	‡The UTOPIA peripheral exists and is muxed on C6415 and C6416
	(C6416 DSP only)
Timer 1		DSPs. The PCI peripheral exists on C6411, C6415 and C6416 DSPs.
Timer 1	TCP†	*EMIFB and McBSP2 are not available on the C6411 DSP.
	TCP†	*EMIFB and McBSP2 are not available on the C6411 DSP.
	(C6416 DSP only)	§EMIFA is only 32 bits on the C6411 DSP.
Timer 2	(C6416 DSP only)	§EMIFA is only 32 bits on the C6411 DSP.
Timer 2		L1 Cache Direct Mapped, 16 KBytes Total

EMIFA (64 Bits)§

	EMIFB (16 Bits)*	EnhancedDMA ControllerChannel)(64	L2Cache/Memory KBytesBanks,1024,4	L1 S1 M1 D1	D2 M2 S2 L2	ControlInterrupt
				TMS320C64x™ DSP Core
	McBSP 0			Instruction Fetch	Control Registers
	McBSP 1			Instruction Dispatch	Advanced
‡				Instruction Decode	In-Circuit Emulation
‡				Data Path A	Data Path B
	UTOPIA Slave			Data Path A	Data Path B
	UTOPIA Slave
				Register File A	Register File B
	McBSP 2*
	PCI		Total
‡	or		Total
‡	HPI 32/16

GPIO[15:9]			L1D Cache 2-Way Set Associative, 16 KBytes Total
GPIO[15:9]

GPIO[8:0]	JTAG	Power
	Emulation	Down	PLL
Interrupt Selector	Control	Logic

The 600-MHz C64x DSPs offer 10× the performance of other DSPs for broadband applications, up to 15× the performance for advanced imaging/video applications and over 18× the performance for 3G

www.dspvillage.ti.com/c6000

TMS320DM642 DSP Block Diagram

	EMIFA 64
	EMIFA 64

	IIC

	VCXO

		L1P Cache Direct Mapped, 16 KBytes Total
	20-Bit	L1P Cache Direct Mapped, 16 KBytes Total
Video Port 0 (VP0)

	10-Bit VP0	TMS320C64x™ DSP Core
	10-Bit VP0	TMS320C64x™ DSP Core

and/or			Instruction Fetch	Control Registers
McBSP0	EnhancedControllerChannel)DMA (64	Cache/MemoryL2 KBytesotal256T,	L1D Cache 2-Way Set Associative, 16 KBytes Total		ControlInterrupt
and/or	EnhancedControllerChannel)DMA (64	Cache/MemoryL2 KBytesotal256T,	L1D Cache 2-Way Set Associative, 16 KBytes Total		ControlInterrupt
and/or			Instruction Dispatch	Advanced
McASP0 Control			Instruction Decode	In-Circuit Emulation
			Data Path A	Data Path B
20-Bit			Register File A	Register File B
Video Port 1 (VP1)
10-Bit VP1			L1 S1 M1 D1	D2 M2 S2 L2
and/or
McBSP1
McASP0 Data

	Power		Timer 0	GPIO16
20-Bit	Power		Timer 0	GPIO16
Video Port 2 (VP2)	Down	PLL
	Logic		Timer 1
PCI-66 MHz
PCI-66 MHz	JTAG		Timer 2
			Timer 2

HPI-32	Emulation
HPI-32	Emulation

Control

or HPI16

and

EMAC

MDIO

The new TMS320DM642 Digital Media processor gives designers the industry's most powerful, flexible and easy-to-use solution for highperformance digital media applications.

C6000 DSP

TMS320C64x™ DSP Generation Product Specification Guide – Fixed-Point DSPs

		Internal RAM (Bits)									Typical Activity
		L1 Program Cache/		Enhanced							Total Internal
		L1 Data Cache/		DMA					Cycle		Power (W) (Full	Voltage (V)			$U.S./1KU+‡	$U.S./10KU+‡
	Device	L2 Unified RAM/Cache	McBSP	(Channels)		COM°	Timers	MHz	(ns)	MIPS	Device Speed)	Core	I/O	Packaging	$U.S./1KU+‡	$U.S./10KU+‡
	TMS320C6416-600	128K/128K/8M	2+UTOPIA*	64		PCI/HPI 32/16	3	600	1.67	4800**	1.06	1.4	3.3	532 BGA, 23 mm	161.92	149.99

	TMS320C6416-500	128K/128K/8M	2+UTOPIA*	64		PCI/HPI 32/16	3	500	2	4000**	0.64	1.2	3.3	532 BGA, 23 mm	117.66	108.99
	TMS320C6415-600	128K/128K/8M	2+UTOPIA*	64		PCI/HPI 32/16	3	600	1.67	4800	1.06	1.4	3.3	532 BGA, 23 mm	145.73	134.99

	TMS320C6415-500	128K/128K/8M	2+UTOPIA*	64		PCI/HPI 32/16	3	500	2	4000	0.64	1.2	3.3	532 BGA, 23 mm	106.86	98.99
	TMS320C6414-600	128K/128K/8M	3	64		HPI 32/16	3	600	1.67	4800	1.06	1.4	3.3	532 BGA, 23 mm	119.82	110.99

	TMS320C6414-500	128K/128K/8M	3	64		HPI 32/16	3	500	2	4000	0.64	1.2	3.3	532 BGA, 23 mm	97.15	89.99
New	TMS320C6411-300	128K/128K/2M	2	64		PCI/HPI 32/16	2	300	3.3	2400	0.25	1.0	3.3	532 BGA, 23 mm	42.21	39.10
	TMS320DM642-600	128K/128K/2M	2§	64	PCI/HPI/EMAC†		3	600	1.67	4800	1.06	1.4	3.3	538 BGA, 23 mm	65.51	60.68
New	TMS320DM642-600	128K/128K/2M	2§	64	PCI/HPI/EMAC†		3	600	1.67	4800	1.06	1.4	3.3	538 BGA, 23 mm	65.51	60.68
New	TMS320DM642-500	128K/128K/2M	2§	64	PCI/HPI/EMAC†		3	500	2	4000	0.64	1.2	3.3	538 BGA, 23 mm	48.53	44.95

‡ Pricing is for TMS devices only.

*UTOPIA pins muxed with a third McBSP.

**Plus on-chip Turbo (TCP) and Viterbi (VCP) coprocessors. ° HPI is selectable, 32-bit or 16-bit.

§ The DM642 can be configured to have up to three serial ports in various video/McASP/McBSP combinations.

† The DM642 can be configured to have either a 32-bit, 66-MHz PCI or 32-bit HPI, or a 16-bit HPI with Ethernet MAC.

A third timer is present but not pinned out.

+ Prices are quoted in US dollars and represent year 2002 suggested resale pricing. Note: Production quantities scheduled for 4Q02.

www.dspvillage.ti.com/c6000

TMS320C62x™ DSP Generation, Fixed Point

TMS320C67x™ DSP Generation, Floating Point

High Performance DSPs

Specifications

•100% code compatible DSPs: Fixed-point C62x™ DSP—16- bit multiply, 32-bit instructions and Floating-point C67x™ DSP—32-bit instructions, single and double precision

•Four data memory access (DMA) channels with bootloading capability (enhanced DMA with 16 channels for C6211, C6711, C6712 and C6713 DSPs)

•Up to 7 Mbit on-chip memory

•Two multi-channel buffered serial ports (McBSPs) (three McBSPs for C6202 and C6203)

•16-bit host-port interface (HPI)

(32-bit Expansion Bus for C6202, C6203 and C6204 DSPs)

•Two 32-bit timers

•32-bit PCI interface (C6205 only)

•Up to 2400 MIPS at 300 MHz

(C6203 DSP)

C67x™ DSP only:

•IEEE floating-point format

•Up to 1350 MFLOPS at 225 MHz

•Two new multi-channel audio serial ports (McASP) (C6713 DSP) can support up to 16 stereo channels of I2S and are compatible with S/PDIF transmit protocol

Applications

•Pooled modems

•Digital Subscriber Line (xDSL)

•Wireless basestations

•Central office switches

•Private Branch Exchange (PBX)

•Digital imaging

•Call processing

•3D graphics

•Speech recognition

•Voice over packet

Features

•C6000™ DSP Platform VelociTI™ advanced VLIW architecture

•Up to eight 32-bit instructions executed each cycle

•Eight independent, multipurpose functional units and thirty-two 32-bit registers

•Industry’s most advanced DSP C compiler and Assembly Optimizer maximize efficiency

TMS320C6201/C6701/C6202/C6203/C6204/C6205 DSP Block Diagram

	Program RAM/Cache/32-Bit Address			Data RAM/32-Bit Address		JTAG
	See Product Specification Guide for			See Product Specification Guide for		Emulation
	Device Memory Size			Device Memory Size		Control
EMIF
20
A		Program/Data Buses				Multi-channel
						Multi-channel
						(T1/E1)
						(T1/E1)
32						Buffered Serial Port 0
32
	C62x™/C67x™ CPU Core			DMA		Multi-channel
						(T1/E1)
	Program Fetch		Control	Ch 0	Bus	Buffered Serial Port 1
	Program Fetch		Control	Ch 0
	Instruction Dispatch		Registers
	Instruction Dispatch		Registers	Ch 1	Peripheral	Buffered Serial Port 2
			Logic		Peripheral	Buffered Serial Port 2
	Instruction Decode		Control			Multi-channel
	Instruction Decode		Control	Ch 2		(T1/E1)
Data Path A		Data Path B		Ch 3		(C6202/C6203 only)
A Register File		B Register File	Test	Aux Ch
A Register File		B Register File		Aux Ch		Timer 0
			In-Circuit			Timer 0
			In-Circuit
L1	S1 M1 D1	D2 M2 S2 L2	Emulation			Timer 1
L1	S1 M1 D1	D2 M2 S2 L2	Interrupts			Timer 1
			Interrupts
						Host Port Interface/
						16-Bit (C6201/C6701)
						or
		PLL Clock Generator	Power Down Modes			Expansion Bus/32-Bit
		PLL Clock Generator	Power Down Modes			(C6202/C6203/C6204)
						or
						PCI Interface
						(C6205)

The fixed-point C6201 DSP is pin-for-pin compatible with the floating-point C6701 DSP offering easy code transfer resulting in significant savings in development, resource and manufacturing costs. Pin compatibility between the C6202, C6203 and C6204 DSPs allow for easy migration between several memory, price and performance options. The C6205 DSP is the first TI DSP with on-chip PCI.

TMS320C6211/C6711/C6712*/C6713 DSP Block Diagram

L1P Cache				JTAG
Direct Mapped				JTAG
Direct Mapped				Emulation
4 KBytes Total				Emulation
4 KBytes Total				Control
				Control

								20
							External
	C62x™/C67x™ CPU Core					Enhanced DMA	Memory
	Program Fetch					Controller	Interface
	Program Fetch			Control				32
	Instruction Dispatch			Registers		16 Channels	Multi-channel
	Instruction Dispatch			Registers	L2 Memory			(T1/E1)
	Instruction Decode			Control	L2 Memory		Buffered Serial Port 0†
	Instruction Decode			Control	4 Way/Banks		Buffered Serial Port 0†
Data Path 1		Data Path 2		Logic	64 KBytes Total	69 Additional		or
Data Path 1		Data Path 2			64 KBytes Total	Transfers	McASP 0
				Test	(C6211, C6711)	Transfers	McASP 0
A Register File		B Register File		Test	(C6211, C6711)
A Register File		B Register File
				In-Circuit	(256 KBytes for		Multi-channel
				Emulation	C6713)		Multi-channel
L1	S1 M1 D1	D2 M2 S2	L2	Emulation	C6713)			(T1/E1)
L1	S1 M1 D1	D2 M2 S2	L2	Interrupts		†	Buffered Serial Port 1†
				Interrupts		Host Port Interface
						16-bit		or
								or
						or		IIC 1
		L1D Cache				GPIO	C6713 only
	2 Way Set Associative					McASP 1
		4 KBytes Total				McASP 1	Timer 0	Timer 1
						IIC 0	Power Down Modes
						C6713 only	Power Down Modes
						C6713 only
							PLL Clock Generator

The C6211 and C6711 DSPs’ innovative two-level cache memory structure enables a breakthrough in system cost/performance. *The C6712 DSP features a 16-bit EMIF and no HPI. All C6x1x devices are pin compatible. The C6713 DSP is a superset of the C6711 DSP and will include I2S, I2C and S/PDIF

enhanced memory space.

www.dspvillage.ti.com/c6000

TMS320C62x™ DSP Generation Product Specification Guide – Fixed-Point DSPs

										Typical Activity
		RAM (bits)						Cycle		Total Internal Power	Voltage (V)					$U.S./1KU+	$U.S./10KU+
	Device	Data	Prog	McBSP	DMA	COM	MHz	(ns)	MIPS	(W) (Full Device Speed)	Core	I/O	Packaging			$U.S./1KU+	$U.S./10KU+
	TMS320C6211B-167	32K/32K/512K*		2	16†	HPI/16	167	6	1336	1.0	1.8	3.3	256	BGA,	27 mm	26.93	24.94
	TMS320C6211B-150	32K/32K/512K*		2	16†	HPI/16	150	6.7	1200	0.9	1.8	3.3	256	BGA,	27 mm	21.54	19.95
	TMS320C6205-200	512K	512K	2	4	PCI/32	200	5	1600	0.8	1.5	3.3	288 BGA, 16 mm			10.74	9.95
	TMS320C6204-200	512K	512K	2	4	Exp. Bus/32	200	5	1600	0.8	1.5	3.3	340 BGA, 18 mm			22.03	20.40
													288 BGA, 16 mm			9.95	9.22
	TMS320C6203B-300	4M	3M	3	4	Exp. Bus/32	300	3.3	2400	1.3	1.5	3.3	352	BGA,	27 mm	110.08	101.97
													384 BGA,		18 mm
	TMS320C6203B-250	4M	3M	3	4	Exp. Bus/32	250	4	2000	1.1	1.5	3.3	352	BGA,	27 mm	84.18	77.98
													384 BGA,		18 mm
New	TMS320C6202B-300	1M	2M	3	4	Exp. Bus/32	300	3.3	2400	1.0	1.5	3.3	352	BGA,	27 mm	78.33	72.56
													384 BGA,		18 mm
New	TMS320C6202B-250	1M	2M	3	4	Exp. Bus/32	250	4	2000	0.9	1.5	3.3	352	BGA,	27 mm	67.14	62.20
													384 BGA,		18 mm
	TMS320C6202-250	1M	2M	3	4	Exp. Bus/32	250	4	2000	2.1	1.8	3.3	352	BGA,	27 mm	110.08	101.97
													384 BGA,		18 mm
	TMS320C6202-200	1M	2M	3	4	Exp. Bus/32	200	5	1600	1.7	1.8	3.3	352	BGA,	27 mm	94.03	87.10
													384 BGA,		18 mm
	TMS320C6201-200	512K	512K	2	4	HPI/16	200	5	1600	1.3	1.8	3.3	352	BGA,	35/27 mm	82.70	76.61

* The C6211 DSP’s 576 Kbits of cache memory is comprised of 32 Kbits data cache, 32 Kbits program cache and 512 Kbits unified cache memory.

† Enhanced DMA.

+ Prices are quoted in U.S. dollars for TMS devices only and represent year 2002 suggested resale pricing. Note: All devices include two timers.

C6000 DSP

TMS320C67x™ DSP Generation Product Specification Guide – Floating-Point DSPs

New

									Typical Activity
	RAM (bits)						Cycle		Total Internal Power	Voltage (V)				$U.S./1KU+	$U.S./10KU+
Device	Data	Prog	McBSP	DMA	COM	MHz	(ns)	MFLOPS	(W) (Full Device Speed)	Core	I/O	Packaging		$U.S./1KU+	$U.S./10KU+
TMS320C6713-225	32K/32K/2M*		2#	16°	HPI/16	225	4.4	1350	1.2	1.2	3.3	272	BGA, 27 mm	28.99	26.85
TMS320C6713-150	32K/32K/2M*		2#	16°	HPI/16	150	6.7	900	1.1	1.2	3.3	208	TQFP, 28 mm	22.35	20.45
TMS320C6712C-150‡	32K/32K/512K*		2	16°	HPI/16	150	6.7	900	0.5	1.2	3.3	272	BGA, 27 mm	14.95	13.50
TMS320C6712-100	32K/32K/512K*		2	16°	–	100	10	600	0.8	1.8	3.3	256	BGA, 27 mm	18.06	16.73
TMS320C6711C-200§	32K/32K/512K*		2	16°	HPI/16	200	5	1200	0.7	1.2	3.3	272	BGA, 27 mm	21.55	18.65
TMS320C6711B-150	32K/32K/512K*		2	16°	HPI/16	150	6.7	900	1.1	1.8	3.3	256	BGA, 27 mm	30.77	28.50
TMS320C6711B-100	32K/32K/512K*		2	16°	HPI/16	100	10	600	0.8	1.8	3.3	256	BGA, 27 mm	21.54	19.95
TMS320C6701-167	512K	512K	2	4	HPI/16	167	6	1000	1.4	1.9	3.3	352	BGA, 35 mm	119.09	110.65
TMS320C6701-150	512K	512K	2	4	HPI/16	150	6.7	900	1.3	1.8	3.3	352	BGA, 35 mm	82.70	76.61

* The C6711 DSP’s 576 Kbits of cache memory is comprised of 32 Kbits data cache, 32 Kbits program cache and 512 Kbits unified cache memory. ° Enhanced DMA.

§ Samples scheduled for 4Q02.

‡ Samples scheduled for 1Q03.

#The C6713 DSP can be configured to have up to three serial ports in various McASP/McBSP combinations by not utilizing the HPI. Other configurable serial options include I2C and additional GPIO.

+Prices are quoted in U.S. dollars and represent year 2002 suggested resale pricing.

Note: All devices include two timers.

www.dspvillage.ti.com/c6000

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