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INTEGRATED CIRCUITS

DATA SHEET

PCD8544

48 × 84 pixels matrix LCD controller/driver

Product specification

 

1999 Apr 12

File under Integrated Circuits, IC17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Philips Semiconductors

Product specification

 

 

48 × 84 pixels matrix LCD controller/driver

PCD8544

 

 

 

 

CONTENTS

1FEATURES

2GENERAL DESCRIPTION

3APPLICATIONS

4ORDERING INFORMATION

5BLOCK DIAGRAM

6PINNING

6.1Pin functions

6.1.1R0 to R47 row driver outputs

6.1.2C0 to C83 column driver outputs

6.1.3VSS1, VSS2: negative power supply rails

6.1.4VDD1, VDD2: positive power supply rails

6.1.5VLCD1, VLCD2: LCD power supply

6.1.6T1, T2, T3 and T4: test pads

6.1.7SDIN: serial data line

6.1.8SCLK: serial clock line

6.1.9D/C: mode select

6.1.10SCE: chip enable

6.1.11OSC: oscillator

6.1.12RES: reset

7

FUNCTIONAL DESCRIPTION

7.1Oscillator

7.2Address Counter (AC)

7.3Display Data RAM (DDRAM)

7.4Timing generator

7.5Display address counter

7.6LCD row and column drivers

7.7Addressing

7.7.1Data structure

7.8Temperature compensation

8 INSTRUCTIONS

8.1Initialization

8.2Reset function

8.3Function set

8.3.1Bit PD

8.3.2Bit V

8.3.3Bit H

8.4Display control

8.4.1Bits D and E

8.5Set Y address of RAM

8.6Set X address of RAM

8.7Temperature control

8.8Bias value

8.9Set VOP value

9LIMITING VALUES

10HANDLING

11DC CHARACTERISTICS

12AC CHARACTERISTICS

12.1Serial interface

12.2Reset

13APPLICATION INFORMATION

14BONDING PAD LOCATIONS

14.1Bonding pad information

14.2Bonding pad location

15TRAY INFORMATION

16DEFINITIONS

17LIFE SUPPORT APPLICATIONS

1999 Apr 12

2

Philips Semiconductors

Product specification

 

 

48 × 84 pixels matrix LCD controller/driver

PCD8544

 

 

1 FEATURES

Single chip LCD controller/driver

48 row, 84 column outputs

Display data RAM 48 × 84 bits

On-chip:

Generation of LCD supply voltage (external supply also possible)

Generation of intermediate LCD bias voltages

Oscillator requires no external components (external clock also possible).

2 GENERAL DESCRIPTION

The PCD8544 is a low power CMOS LCD controller/driver, designed to drive a graphic display of 48 rows and

84 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption.

The PCD8544 interfaces to microcontrollers through a serial bus interface.

The PCD8544 is manufactured in n-well CMOS technology.

External

RES

(reset) input pin

 

 

Serial interface maximum 4.0 Mbits/s

3

APPLICATIONS

CMOS compatible inputs

Telecommunications equipment.

 

 

 

 

Mux rate: 48

Logic supply voltage range VDD to VSS: 2.7 to 3.3 V

Display supply voltage range VLCD to VSS

6.0 to 8.5 V with LCD voltage internally generated (voltage generator enabled)

6.0 to 9.0 V with LCD voltage externally supplied (voltage generator switched-off).

Low power consumption, suitable for battery operated systems

Temperature compensation of VLCD

Temperature range: 25 to +70 °C.

4 ORDERING INFORMATION

TYPE NUMBER

 

PACKAGE

 

 

 

 

NAME

DESCRIPTION

VERSION

 

 

 

 

 

PCD8544U

chip with bumps in tray; 168 bonding pads + 4 dummy pads

 

 

 

 

1999 Apr 12

3

Philips Semiconductors

Product specification

 

 

48 × 84 pixels matrix LCD controller/driver

PCD8544

 

 

5 BLOCK DIAGRAM

 

 

 

C1 to C83

 

R0 to R47

 

 

BIAS

COLUMN DRIVERS

ROW DRIVERS

 

 

 

 

 

 

 

VLCD2

VOLTAGE

 

 

 

 

 

 

GENERATOR

 

 

 

 

 

 

 

DATA LATCHES

 

SHIFT REGISTER

 

 

 

 

 

 

RESET

RES

 

VLCD

 

 

 

OSCILLATOR

OSC

VLCD1

 

 

 

 

 

GENERATOR

DISPLAY DATA RAM

 

 

 

 

 

 

 

(DDRAM)

 

TIMING

 

 

 

 

48 × 84

 

 

 

 

 

 

GENERATOR

 

VDD1 to VDD2

 

 

 

 

 

 

 

 

 

 

 

VSS1 to VSS2

 

 

 

 

DISPLAY

 

 

 

 

 

 

 

 

 

ADDRESS COUNTER

ADDRESS

 

T1

 

COUNTER

 

 

 

 

 

 

T2

 

 

 

 

 

 

T3

DATA

 

 

PCD8544

 

REGISTER

 

 

 

 

 

 

 

 

T4

 

 

 

 

 

 

 

 

I/O BUFFER

 

 

 

 

 

 

 

 

MGL629

 

 

SDIN

SCLK

D/C

SCE

 

 

Fig.1 Block diagram.

1999 Apr 12

4

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