A.4 MC68040 PROCESSORS

Table A-10. MC68040 Instruction Set

Description

Add Decimal with Extend

Add

Add Address

Add Immediate

Add Quick

Add with Extend

Logical AND

Logical AND Immediate

AND Immediate to Condition Code Register

AND Immediate to Status Register

Arithmetic Shift Left and Right

Branch Conditionally

Test Bit and Change

Test Bit and Clear

Test Bit Field and Change

Test Bit Field and Clear

Signed Bit Field Extract

Unsigned Bit Field Extract

Bit Field Find First One

Bit Field Insert

Test Bit Field and Set

Test Bit Field

Breakpoint

Branch

Test Bit and Set

Branch to Subroutine

Test Bit

Compare and Swap Operands

Compare and Swap Dual Operands

Check Register Against Bound

Check Register Against Upper and Lower Bounds

Invalidate Cache Entries

Clear

Compare

Compare Address

Mnemonic

Description

CMPI

Compare Immediate

CMPM

Compare Memory to Memory

CMP2

Compare Register Against Upper and Lower Bounds

CPUSH

Push then Invalidate Cache Entries

DBcc

Test Condition, Decrement and Branch

DIVS, DIVSL

Signed Divide

DIVU, DIVUL

Unsigned Divide

EOR

Logical Exclusive-OR

EORI

Logical Exclusive-OR Immediate

EORI to CCR

Exclusive-OR Immediate to Condition Code Register

EORI to SR

Exclusive-OR Immediate to Status Register

EXG

Exchange Registers

EXT, EXTB

Sign Extend

FABS1

Floating-Point Absolute Value

FSABS, FDABS1

Floating-Point Absolute Value (Single/Double Precision)

FACOS1,2

Floating-Point Arc Cosine

FADD1

Floating-Point Add

FSADD, FDADD1

Floating-Point Add (Single/Double Precision)

FASIN1,2

Floating-Point Arc Sine

FATAN1,2

Floating-Point Arc Tangent

FATANH1,2

Floating-Point Hyperbolic Arc Tangent

FBcc1

Floating-Point Branch

FCMP1

Floating-Point Compare

FCOS1,2

Floating-Point Cosine

FCOSH1,2

Floating-Point Hyperbolic Cosine

FDBcc1

Floating-Point Decrement and Branch

FDIV1

Floating-Point Divide

FSDIV, FDDIV1

Floating-Point Divide (Single/Double Precision)

FETOX1,2

Floating-Point ex

FETOXM11,2

Floating-Point ex - 1

FGETEXP1,2

Floating-Point Get Exponent

FGETMAN1,2

Floating-Point Get Mantissa

FINT1,2

Floating-Point Integer Part

FINTRZ1,2

Floating-Point Integer Part, Round-to-Zero

FLOG101,2

Floating-Point Log10

FLOG21,2

Floating-Point Log2

FLOGN1,2

Floating-Point Loge

FLOGNP11,2

Floating-Point Loge (x + 1)

FMOD1,2

Floating-Point Modulo Remainder

FMOVE1

Move Floating-Point Register

FSMOVE, FDMOVE1

Move Floating-Point Register (Single/Double Precision)

FMOVECR1

Move Constant ROM

FMOVEM1

Move Multiple Floating-Point Registers

FMUL1

Floating-Point Multiply

Floating-Point Multiply (Single/Double Precision)

Table A-10. MC68040 Instruction Set (Continued)

FNEG1

Floating-Point Negate

FSNEG, FDNEG1

Floating-Point Negate (Single/Double Precision)

FNOP1

Floating-Point No Operation

FREM1,2

IEEE Remainder

FRESTORE1

Restore Floating-Point Internal State

FSAVE1

Save Floating-Point Internal State

FSCALE1,2

Floating-Point Scale Exponent

FScc1

Floating-Point Set According to Condition

FSGLDIV1,2

Single-Precision Divide

FSGLMUL1,2

Single-Precision Multiply

FSIN1,2

Sine

FSINCOS1,2

Simultaneous Sine and Cosine

FSINH1,2

Hyperbolic Sine

FSQRT1

Floating-Point Square Root

FSSQRT, FDSQRT1

Floating-Point Square Root (Single/Double Precision)

FSUB1

Floating-Point Subtract

FSSUB, FDSUB1

Floating-Point Subtract (Single/Double Precision)

FTAN1,2

Tangent

FTANH1,2

Hyperbolic Tangent

FTENTOX1,2

Floating-Point 10x

FTRAPcc1,2

Floating-Point Trap On Condition

FTST1

Floating-Point Test

Floating-Point 2x

Take Illegal Instruction Trap

JMP

Jump

JSR

Jump to Subroutine

LEA

Load Effective Address

LINK

Link and Allocate

LSL, LSR

Logical Shift Left and Right

MOVE

Move

MOVEA

Move Address

MOVE from CCR

Move from Condition Code Register

MOVE to CCR

Move to Condition Code Register

MOVE from SR

Move from Status Register

MOVE to SR

Move to Status Register

MOVE USP

Move User Stack Pointer

MOVEC

Move Control Register

MOVEM

Move Multiple Registers

MOVEP

Move Peripheral

MOVEQ

Move Quick

MOVES

Move Alternate Address Space

MOVE16

16-Byte Block Move

MULS

Signed Multiply

MULU

Unsigned Multiply

Description

NBCD

Negate Decimal with Extend

NEG

Negate

NEGX

Negate with Extend

NOP

No Operation

NOT

Logical Complement

OR

Logical Inclusive-OR

ORI

Logical Inclusive-OR Immediate

ORI to CCR

Inclusive-OR Immediate to Condition Code Register

ORI to SR

Inclusive-OR Immediate to Status Register

PACK

Pack BCD

PEA

Push Effective Address

PFLUSH

Flush Entry(ies) in the ATCs

PFLUSHA

Flush all Entry(ies) in the ATCs

PTEST

Test a Logical Address

RESET

Reset External Devices

ROL, ROR

Rotate Left and Right

ROXL, ROXR

Rotate with Extend Left and Right

RTD

Return and Deallocate

RTE

Return from Exception

RTR

Return and Restore

RTS

Return from Subroutine

SBCD

Subtract Decimal with Extend

Scc

Set Conditionally

STOP

Stop

SUB

Subtract

SUBA

Subtract Address

SUBI

Subtract Immediate

SUBQ

Subtract Quick

SUBX

Subtract with Extend

SWAP

Swap Register Words

TAS

Test Operand and Set

TRAP

Trap

TRAPcc

Trap Conditionally

TRAPV

Trap on Overflow

TST

Test Operand

UNLK

Unlink

UNPK

Unpack BCD