Output Clocks

BUFR

A BUFR is likely to be most effective when it meets the following criteria:

•The BUFR is an externally generated clock.

•The BUFR is under 200 MHz.

•The BUFR is required to source up to a maximum of three clock regions.

BUFMRCE

A BUFMRCE might be required for a Virtex-7 device in order to use this technique with more than one clock region (but only up to three vertically adjacent regions).

BUFHCE

A BUFHCE is better suited for higher speed clocks that can be contained in a single clock region.

BUFGCE

Although a BUFGCE can span the device, and is the most flexible, it is not the best choice for optimal power savings.

Output Clocks

Using an ODDR component is an effective way to forward a clock out of an FPGA device for external clocking devices.

To create a clock that is well controlled with respect to phase relationship and duty cycle:

1.Tie one input high.

2.Tie the other input low.

Use the set/reset and clock enable to stop the clock and hold it at a certain polarity for sustained amounts of time.

If further phase control is necessary for an external clock, use an MMCM or PLL with either or both of the following:

•External feedback compensation

•Phase compensation that is:

•Coarse or fine grained

•Fixed or variable

This gives control over clock phase and propagation times to other devices, thereby simplifying external timing requirements from the device.

UG872 (v14.3) October 16, 2012