Chapter 5

Clocking

The design decisions you make before the first synthesis run, or even before you write the first line of HDL code, can significantly impact your design goals. Smart planning and a small additional investment of time early on ensures good up front decisions and saves project time.

Selecting Clocking Resources

Xilinx® recommends that you select clocking resources as one of the first steps of your design, well before pinout selection. Your clocking selections can dictate a particular pinout, and can also direct logic placement for that logic. Proper clocking selections can yield superior results.

Virtex®-6 and Virtex-7 architectures contain 32 global clock buffers known as BUFG.

BUFG can meet most clocking requirements for designs with less demanding requirements with respect to:

•Number of clocks

•Design performance

•Low power demands

•Other clocking characteristics such as:

•Clock gating

•Multiplexing

•Other clocking control

BUFG components are easily inferred by synthesis, and have few restrictions, allowing for most general clocking.

However, if clocking demands exceed the capabilities of BUFG, or if better clocking characteristics are desired, Xilinx recommends that you:

1.Analyze the clocking needs against the available clock-in resources.

2.Select and control the best resource for the task.

UG872 (v14.3) October 16, 2012