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Comments

/* Comment here

Comment here */

// Comment here

Compiler directives

  • `include can be used to insert the contents of a seperate file into a module.

`include "<file_name>"

  • `timescale is a compiler directive that indicates to the simulator the time units and precision to be used during simulation.

`timescale <units> / <precision>

Example: `timescale 1 ns / 1ps

  • `define is a compiler directive that defines a value to a variable. That variable can then be called upon in the code by referencing the `name of the specified variable.

`define <name> <string>

  • `ifdef is a compiler directive that checks for the existence of a specified `define and then conditionally includes a section of code during compilation if it exists.

`ifdef <define_name>

<statements>;

`elsif <define_name>

<statements>;

`endif

  • `ifndef is the opposite of `ifdef in that if a `define was not declared, it includes a section of code.

`ifndef <define_name>

<statements>;

`endif

  • `elsif can be used in conjunction with a `ifdef to find the existence of another `define and conditionally compile a different section of code if the previous conditions were not met and this condition is met.

  • `else also can be used in conjunction with a `ifdef where it will compile a section of code if all previous `ifdef and `elsif conditions were not met.

  • `endif is used at the end of a `ifdef or `ifndef statement to signify the end of the included code.

Example:

`define DATA_WIDTH 16

`define DATA_WIDTH16

reg [`DATA_WIDTH-1:0] data;

`ifdef DATA_WIDTH8

// If DATA_WIDTH8 was set, this would get compiled

`elsif DATA_WIDTH16

// Since DATA_WIDTH16 is set, this does get compiled

`else

// If DATA_WIDTH8 and DATA_WIDTH16 was not defined,

// this would be compiled

`endif

Simulation Constructs

Delays

  • Finite Delay #<delay_value>;

  • Wait for any signal transition @(<signal>);

  • Wait for negative signal transition @(negedge <signal>);

  • Wait for positive signal transition @(posedge <signal>);

  • Wait for signal condition wait (<signal>==<value>);

Loops

  • Decrementing/Incremental for loops

integer <var>;

for (<var> = <initial_value>; <var> >= <final_value>; <var>=<var>-1)

begin

<statement>;

end

  • Disable loop disable <loop_identifier>;

The disable statement terminates the activity associated with currently active procedures.

begin : block_name   rega = regb;   disable block_name;   regc = rega; // this assignment will never execute end

  • Forever loop forever begin <statement>; end

  • Repeat loop repeat (<value>) begin <statements>; end

Executes a statement a fixed number of times.

  • While loop while (<condition>) begin <statement>; end

Procedural Block

  • Conditional repeated execution

always @(<signals>) begin <statements>; end

  • Execution once

Initial begin

// Wait for Global Reset to Complete

#100; <statements>;

end

  • Repeated execution

always begin <statements>; end

Signal assignment

  • Assign a value assign <reg> = <value>;

  • Deassign a value deassign <reg>;

The assign statement is used to express the first type of procedural continuous assignment.

The deassign statement is used to end a procedural continuous assignment.

always @(clear or preset)  if (!clear) assign q = 0  else if (!preset) assign q = 1; else deassign q;

  • Force a value force <wire_or_reg> = <value>;

  • Release a forced value release <wire_or_reg>;

Force is a form of procedural continuous assignment. A force statement to a register will override a procedural assignment or procedural continuous assignment that takes place on the register until a release procedural statement is executed on the register.

module test; reg a, b, c, d; wire e;

and and1 (e, a, b, c);

initial begin  assign d = a & b & c;  a = 1; b = 0; c = 1;  #10;

force d = (a | b | c); force e = (a | b | c);  #10 $stop;  release d;  release e;  #10 $finish; end endmodule

Initialize values

  • Using initial initial begin <reg> = 16'h0000; end

  • Using reg declaration reg [15:0] <name> = 16'h0000;

Signal, Constant and Variable

integer <name>; // 32-bit integer

real <name>; // 64-bit floating point

time <name>; // 64-bit floating point

parameter <name> = <value>;

  • register reg [1:0] <name> = 2'b00;

reg signed [17:0] <name> = 18'h00000;

  • keeper reg trireg [15:0] <name> = 16'h0000; // Stores last value when 3-stated

Clock Stimulus

Ex:1

parameter PERIOD = <value>;

always begin CLK = 1'b0;

#(PERIOD/2) CLK = 1'b1;

#(PERIOD/2);

end

Ex:2

initial begin

CLK = 1'b0;

#(PERIOD/2);

forever

#(PERIOD/2) CLK = ~CLK;

end

System tasks & function

  • Convert to signed value $signed(<signal>);

  • Convert to unsigned value $unsigned(<signal>); ///!!!!!!!

  • Simulation time

initial $timeformat (<unit>, <precision>, <suffix_string>, <min_field_width>);

initial $timeformat (-6, 6, " us", 13);

initial $timeformat (-9, 3, " ns", 13);

initial $timeformat (-12, 1, " ps", 13);

Information on the system tasks $time, $stime, $realtime, and $timeformat

$time is a system function in which returns the current simulation time as a 64-bit integer.

$stime is a system function in which returns the lower 32-bits of the current simulation time.

$realtime is a system function that returns the current simulation time as a real number.

$timeformat is a system call which specifies the format in which the $time, $stime and $realtime should be displayed when used with the %t format variable in a display or write call. It is recommmended to specify this within the testbench when using the %t variable to make the time value more readable. The $timeformat must be specified within an initial declaration.

  • Stop simulation

Pause simulation $stop;

Quit simulation $finish;

  • Random number generation <reg> = $random(<seed>);

  • File I/O

Read memory file (binary/hex)

$readmemb is a system function which will read binary data from a specified file.

$readmemb ("<file_name>", <reg_name>);

$readmemh is the same as $readmemb with the exception that it inputs hex data as the read values.

$readmemh ("<file_name>", <reg_name>);

Ex:

reg [31:0] prom_data [1023:0];

initial

$readmemb ("../data/mem_file.dat", prom_data);

Read/write to a file

Opening Command

$fopen is used to open a file for reading, writing and/or appending. This operation must precede any of the reading or writing commands specified in this document. When using the $fopen, you must specify the file name and file mode (read, write, etc.).

integer <file_desc>;

<file_desc> = $fopen("<file_name>", "<file_mode>");

Upon opening the file, a handle number is issued for the file and must be used to reference the file in subsequent commands. Generally, this number should be assigned to a declared interger.

The file mode can be one of the following:

"r" ...... Open ASCII file for reading

"rb" ..... Open Binary file for reading

"w" ...... Open ASCII file for writing (delete if exists)

"wb" ..... Open Binary file for writing (delete if exists)

"a" ...... Open ASCII file for writing (append to end of file)

"ab" ..... Open Binary file for writing (append to end of file)

"r+" ..... Open ASCII file for reading and writing

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