PCI_22

A message broadcast mechanism used for

communicating processor status and/or (optionally)

logical sideband signaling between PCI agents.

Data in a cache-based system that is no longer valid

and, therefore, must be discarded.

The ability of an agent to spread assertion of qualified

signals over several clocks.

A method of address decoding in which a device

accepts all accesses not positively decoded by another

agent. See also positive decoding.

An agent that responds (with a positive

acknowledgment by asserting DEVSEL#) to a bus

transaction initiated by a master.

A termination mechanism that allows a target to

terminate a transaction in which a fatal error has

occurred, or to which the target will never be able to

respond.

The number of PCI clocks that the target takes to

assert TRDY# for the first data transfer.

The number of PCI clocks that the target takes to

assert TRDY# from the end of the previous data

phase of a burst.

A transaction termination brings bus transactions to

an orderly and systematic conclusion. All

transactions are concluded when FRAME# and

IRDY# are deasserted (an idle cycle). Termination

may be initiated by the master or the target.

An address phase plus one or more data phases.

A bus cycle used to prevent contention when one

agent stops driving a signal and another agent begins

driving it. A turnaround cycle must last one clock

and is required on all signals that may be driven by

more than one agent.

A bus clock in which no transfer occurs.