PCI_22

CP

Extended Capability

RV

Checksum and

Reserved

Bus support functions supplied by the host system,

typically in a PCI compliant bridge or standard

chipset.

See bus command.

A set of 64 registers (DWORDs) used for

configuration, initialization, and catastrophic error

handling. This address space consists of two regions:

a header region and a device-dependent region.

Bus transaction used for system initialization and

configuration via the configuration address space.

Dual address cycle. A PCI transaction where a 64-bit

address is transferred across a 32-bit data path in two

clock cycles. See also SAC.

When two devices (one a master, the other a target)

require the other device to respond first during a

single bus transaction. For example, a master

requires the addressed target to assert TRDY# on a

write transaction before the master will assert IRDY#.

(This behavior is a violation of this specification.)

The process of a target latching a request and

completing it after the master was terminated with

Retry.

See PCI device.

The last 48 DWORDS of the PCI configuration space.

The contents of this region are not described in this

document.

When this timer expires, a device is permitted to

discard unclaimed Delayed Completions (refer to

Section 3.3.3.3.3. and Appendix E).

A 32-bit block of data.

Extended Industry Standard Architecture expansion

bus, based on the IBM PC AT bus, but extended to 32

bits of address and data.

A circuit board that plugs into a motherboard and

provides added functionality.

A bridge that has PCI as its primary interface and

ISA, EISA, or Micro Channel as its secondary

interface. This specification does not preclude the use

of bridges to other buses, although deadlock and other

system issues for those buses have not been

considered.

A set of logic that is represented by a single

Configuration Space.

The first 16 DWORDS of a device’s Configuration

Space. The header region consists of fields that

uniquely identify a PCI device and allow the device to

be generically controlled.

See also device dependent region.

Arbitration that occurs during a previous access so

that no PCI bus cycles are consumed by arbitration,

except when the bus is idle.

A low latency path through which the processor may

directly access PCI devices mapped anywhere in the

memory, I/O, or configuration address spaces.

Any clock period that the bus is idle (FRAME# and

IRDY# deasserted).

The period of time that begins when RST# is

deasserted and completes 225 PCI clocks later.

Industry Standard Architecture expansion bus built

into the IBM PC AT computer.

Pullup resistors or active components that are only

used to sustain a signal state.

See arbitration latency, master data latency, target

initial latency, and target subsequent latency.

A mechanism for ensuring that a bus master does not

extend the access latency of other masters beyond a

specified value.

An agent that initiates a bus transaction.

A termination mechanism that allows a master to

terminate a transaction when no target responds.

The number of PCI clocks until IRDY# is asserted

from FRAME# being asserted for the first data phase

or from the end of the previous data phase.

The Micro Channel architecture expansion bus as

defined by IBM for its PS/2 line of personal

computers.

A circuit board containing the basic functions (e.g.,

CPU, memory, I/O, and expansion connectors) of a

computer.

A device that implements from two to eight functions.

Each function has its own Configuration Space that is

addressed by a different encoding of AD[10::08]

during the address phase of a configuration

transaction.

A single-function device that contains more than one

source of bus master activity. For example, a device

that has a receiver and transmitter that operate

independently.

Non-maskable interrupt.

A logical sequence of transactions, e.g., Lock.

An electrical drive element (transistor) for a single

signal on a PCI device.

An expansion connector that conforms to the

electrical and mechanical requirements of the PCI

local bus standard.

A device that (electrical component) conforms to the

PCI specification for operation in a PCI local bus

environment.

Pin grid array component package.

One or more clocks in which a single unit of

information is transferred, consisting of:

∙ an address phase (a single address transfer in one

clock for a single address cycle and two clocks

for a dual address cycle)

∙ a data phase (one transfer state plus zero or more

wait states)

A method of address decoding in which a device

responds to accesses only within an assigned address

range. See also subtractive decoding.

Power-on self test. A series of diagnostic routines

performed when a system is powered up.

Resistors used to insure that signals maintain stable

values when no agent is actively driving the bus.

The time that follows Initialization Time.

Single address cycle. A PCI transaction where a

32-bit address is transferred across a 32-bit data path

in a single clock cycle. See also DAC.

An arrangement on a PCI motherboard that allows a

PCI connector to share the system bus slot nearest the

PCI bus layout with an ISA, EISA, or MC bus

connector. In an MC system, for example, the shared

slot can accommodate either an MC expansion board

or a PCI expansion board.

A device that contains only one function.

Any signal not part of the PCI specification that

connects two or more PCI-compliant agents and has

meaning only to those agents.