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7.6.5. Vendor Provided Specification

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7.6.6. Recommendations

7.6.6.1. Pinout Recommendations

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7.6.6.2. Clocking Recommendations

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231

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66 MHz

Device A

PCI Add-in

Connector

66 MHz

Device B

66 MHz

Device C

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7.7. System (Planar) Specification

7.7.1. Clock Uncertainty

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53 The system designer must address an additional source of clock skew. This clock skew occurs between two components that have clock input trip points at opposite ends of the Vil - Vih range. In certain circumstances, this can add to the clock skew measurement as described here. In all cases, total clock skew must be limited to the specified number.

232

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7.7.2. Reset

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7.7.3. Pullups

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7.7.4. Power

7.7.4.1. Power Requirements

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7.7.4.2. Sequencing

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7.7.4.3. Decoupling

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7.7.5. System Timing Budget

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NOTES:

1.The 50 MHz example is shown for example purposes only.

2.These times are computed. The other times are fixed. Thus, slowing down the bus clock enables the system manufacturer to gain additional distance or add additional loads. The component specifications are required to guarantee operation at 66 MHz.

3Clock skew specified here includes all sources of skew. If spread spectrum clocking (SSC) is used on the system board, the maximum clock skew at the input of the device on an expansion board includes SSC tracking skew.

7.7.6.Physical Requirements

7.7.6.1. Routing and Layout Recommendations for Four-Layer Boards

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7.7.6.2. Planar Impedance

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7.7.7. Connector Pin Assignments

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7.8. Expansion Board Specifications

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54 As a general rule, there will be only one such connector, but more than one are possible in certain cases.

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