PCI_22

Revision 2.2

asserted when they appear as SIGNAL and will be false or deasserted when they appear as !SIGNAL. Internal signals will be true when they appear as Signal and false when they appear as !Signal. A few of the output enable equations use the "==" symbol to refer to the previous state. For example:

OE[PAR] == [S_DATA * !TRDY# * (cmd=read)]

This indicates the output buffer for PAR is enabled when the previous state is S_DATA, TRDY# is asserted, the transaction is a read. The first state machine presented is for the target, the second is the master. Caution needs to be taken when an agent is both a master and a target. Each must have its own state machine that can operate independently of the other to avoid deadlocks. This means that the target state machine cannot be affected by the master state machine. Although they have similar states, they cannot be built into a single machine.

Note: LOCK# can only be implemented by a bridge; refer to Appendix F for details about the use of LOCK#. For a non-bridge device, the use of LOCK# is prohibited.

B A CK O F F

S _D AT A

Target

T U R N _ A R

Sequencer

Machine

F R E E L O C K E D

Target LOCK Machine

IDLE or TURN_AR -- Idle condition or completed transaction on bus.

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S_DATA -- Agent has accepted request and will respond.

BACKOFF -- Agent busy unable to respond at this time.

Target LOCK Machine

FREE -- Agent is free to respond to all transactions.

LOCKED -- Agent will not respond unless LOCK# is deasserted during the address phase.

Note: If the device does fast decode, OE[PERR#] must be delayed one clock to avoid contention.

When the target supports the Special Cycle command, an additional term must be included to ensure these signals are not enabled during a Special Cycle transaction.

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Definitions

These signals are between the target bus sequencer and the backend. They indicate how the bus sequencer should respond to the current bus operation.

The following paragraphs discuss each state and describe which equations can be removed if some of the PCI options are not implemented.

The IDLE and TURN_AR are two separate states in the state machine, but are combined here because the state transitions are the same from both states. They are implemented as separate states because active signals need to be deasserted before the target tri-states them.

If the target cannot do single cycle address decode, the path from IDLE to S_DATA can be removed. The reason the target requires the path from the TURN_AR state to S_DATA and B_BUSY is for back-to-back bus operations. The target must be able to decode back-to-back transactions.

B_BUSY is a state where the agent waits for the current transaction to complete and the bus to return to the Idle state. B_BUSY is useful for devices that do slow address decode or perform subtractive decode. If the target does neither of these two options, the path to S_DATA and BACKOFF may be removed. The term "!Hit" may be removed from the B_BUSY equation also. This reduces the state to waiting for the current bus transaction to complete.

S_DATA is a state where the target transfers data and there are no optional equations.

BACKOFF is where the target goes after it asserts STOP# and waits for the master to deassert FRAME#.

FREE and LOCKED refer to the state of the target with respect to a lock operation. If the target does not implement LOCK#, then these states are not required. FREE indicates when the agent may accept any request when it is the target. If LOCKED, the target will retry any request when it is the target unless LOCK# is deasserted during the address phase. The agent marks itself locked whenever it is the target of a transaction and LOCK# is deasserted during the address phase. It is a little confusing for the target to lock itself on a transaction that is not locked. However, from an implementation point of view, it is a simple mechanism that uses combinatorial logic and always works. The device will unlock itself at the end of the transaction when it detects FRAME# and LOCK# both deasserted.

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Revision 2.2

The second equation in the goto LOCKED in the FREE state can be removed if fast decode is done. The first equation can be removed if medium or slow decode is done. L_lock# is LOCK# latched during the address phase and is used when the agent’s decode completes.

IDLE

ADDR

DR_BUS

S_TAR

M_DATA

Master LOCK Machine

Master Sequencer Machine

IDLE -- Idle condition on bus.

ADDR -- Master starts a transaction.

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Master LOCK Machine

FREE -- LOCK# is not in use (not owned).

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Revision 2.2

The master of the transaction is responsible to drive the following signals:

Enable the output buffers:

if ADDR drive command

if M_DATA drive byte enables

if DR_BUS if (Step * Request) drive command else drive lines to a valid state

The following signals are generated from state and sampled (not asynchronous) bus signals.

FRAME# = !( ADDR + M_DATA * !Dev_to * {[!Comp * (!To + !GNT#) * STOP#] + !Ready })

IRDY# = ![M_DATA * (Ready + Dev_to)]

REQ# = ![(Request * !Lock_a + Request * Lock_a * FREE) *!(S_TAR * Last State was S_TAR)]

LOCK# = Own_lock * ADDR + Target_abort

+Master_abort + M_DATA * !STOP# * TRDY# * !Ldt

+Own_lock * !Lock_a * Comp * M_DATA * FRAME# * !TRDY#

PAR = even parity across AD[31::00] and C/BE#[3::0] lines. PERR# = R_perr

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Revision 2.2

Definitions

These signals go between the bus sequencer and the backend. They provide information to the sequencer when to perform a transaction and provide information to the backend on how the transaction is proceeding. If a cycle is retried, the backend will make the correct modification to the affected registers and then indicate to the sequencer to perform another transaction. The bus sequencer does not remember that a transaction was retried or aborted but takes requests from the backend and performs the PCI transaction.

The master state machine has many options built in that may not be of interest to some implementations. Each state will be discussed indicating what affect certain options have on the equations.

IDLE is where the master waits for a request to do a bus operation. The only option in this state is the term "Step". It may be removed from the equations if address stepping is not supported. All paths must be implemented. The path to DR_BUS is required to insure that the bus is not left floating for long periods. The master whose GNT# is asserted must go to the drive bus if its Request is not asserted.

ADDR has no options and is used to drive the address and command on the bus.

M_DATA is where data is transferred. If the master does not support fast back-to-back transactions, the path to the ADDR state is not required.

The equations are correct from the protocol point of view. However, compilers may give errors when they check all possible combinations. For example, because of protocol, Comp cannot be asserted when FRAME# is deasserted. Comp indicates the master is in the last data phase, and FRAME# must be deasserted for this to be true.

TURN_AR is where the master deasserts signals in preparation for tri-stating them. The path to ADDR may be removed if the master does not do back-to-back transactions.

S_TAR could be implemented a number of ways. The state was chosen to clarify that "state" needs to be remembered when the target asserts STOP#.

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Revision 2.2

DR_BUS is used when GNT# has been asserted, and the master either is not prepared to start a transaction (for address stepping) or has none pending. If address stepping is not implemented, then the equation in goto DR_BUS that has "Step" may be removed and the goto ADDR equation may also remove "Step".

If LOCK# is not supported by the master, the FREE and BUSY states may be removed. These states are for the master to know the state of LOCK# when it desires to do a locked transaction. The state machine simply checks for LOCK# being asserted. Once asserted, it stays BUSY until FRAME# and LOCK# are both deasserted signifying that LOCK# is now free.

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Revision 2.2

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