PCI_22
.pdf
Revision 2.2
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Master Signals
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e.The master must deassert IRDY# the clock after the completion of the last data phase.
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Target Signals
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$Q DJHQW FODLPV WR EH WKH WDUJHW RI WKH DFFHVV E\ DVVHUWLQJ DEVSEL#
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Data Phases
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Revision 2.2
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DEVSEL#
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Arbitration
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Latency
25.All targets are required to complete the initial data phase of a transaction (read or write) within 16 clocks from the assertion of FRAME#. Host bus bridges have an exception (refer to Section 3.5.1.1.).
56 Higher priority here does not imply a fixed priority arbitration, but refers to the agent that would win arbitration at a given instant in time.
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Revision 2.2
26.The target is required to complete a subsequent data phase within eight clocks from the completion of the previous data phase.
27.A master is required to assert its IRDY# within eight clocks for any given data phase (initial and subsequent).
Device Selection
28.A target must do a full decode before driving/asserting DEVSEL# or any other target response signal.
29.A target must assert DEVSEL# (claim the transaction) before it is allowed to issue any other target response.
30.In all cases except Target-Abort, once a target asserts DEVSEL# it must not deassert DEVSEL# until FRAME# is deasserted (IRDY# is asserted) and the last data phase has completed.
31.A PCI device is a target of a Type 0 configuration transaction (read or write) only if its IDSEL is asserted, and AD[1::0] are “00” during the address phase of the command.
Parity
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33.Only the master of a corrupted data transfer is allowed to report parity errors to software using mechanisms other than PERR# (i.e., requesting an interrupt or asserting SERR#). In some cases, the master delegates this responsibility to a PCI- to-PCI bridge handling posted memory write data. See the PCI-to-PCI Bridge Architecture Specification for details.
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256
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Base Class |
Sub-Class |
Interface |
Meaning |
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00h |
00h |
All currently implemented devices |
00h |
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except VGA-compatible devices |
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01h |
00h |
VGA-compatible device |
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Base Class |
Sub-Class |
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Interface |
Meaning |
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00h |
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00h |
SCSI bus controller |
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01h |
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xxh |
IDE controller (see below) |
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01h |
02h |
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00h |
Floppy disk controller |
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03h |
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00h |
IPI bus controller |
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04h |
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00h |
RAID controller |
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80h |
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00h |
Other mass storage controller |
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258
Revision 2.2
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Base Class |
Sub-Class |
Interface |
Meaning |
|
00h |
00h |
Ethernet controller |
02h |
01h |
00h |
Token Ring controller |
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02h |
00h |
FDDI controller |
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03h |
00h |
ATM controller |
|
04h |
00h |
ISDN controller |
|
80h |
00h |
Other network controller |
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Base Class |
Sub-Class |
Interface |
Meaning |
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00000000b |
VGA-compatible controller. Memory |
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addresses 0A0000h through |
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0BFFFFh. I/O addresses 3B0h to |
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3BBh and 3C0h to 3DFh and all |
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aliases of these addresses. |
03h |
00h |
00000001b |
8514-compatible controller -- 2E8h |
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and its aliases, 2EAh-2EFh |
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01h |
00h |
XGA controller |
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02h |
00h |
3D controller |
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80h |
00h |
Other display controller |
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Base Class |
Sub-Class |
Interface |
Meaning |
|
00h |
00h |
Video device |
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01h |
00h |
Audio device |
04h |
02h |
00h |
Computer telephony device |
|
80h |
00h |
Other multimedia device |
259
Revision 2.2
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Base Class |
Sub-Class |
Interface |
Meaning |
|
00h |
00h |
RAM |
05h |
01h |
00h |
Flash |
|
80h |
00h |
Other memory controller |
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Base Class |
Sub-Class |
Interface |
Meaning |
|
00h |
00h |
Host bridge |
|
01h |
00h |
ISA bridge |
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02h |
00h |
EISA bridge |
06h |
03h |
00h |
MCA bridge |
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00h |
PCI-to-PCI bridge |
|
04h |
01h |
Subtractive Decode PCI-to-PCI |
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bridge. This interface code identifies |
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the PCI-to-PCI bridge as a device that |
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supports subtractive decoding in |
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addition to all the currently defined |
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functions of a PCI-to-PCI bridge. |
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05h |
00h |
PCMCIA bridge |
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06h |
00h |
NuBus bridge |
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07h |
00h |
CardBus bridge |
|
08h |
xxh |
RACEway bridge (see below) |
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80h |
00h |
Other bridge device |
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