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7.3. Device Implementation Considerations

7.3.1. Configuration Space

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7.4. Agent Architecture

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7.5. Protocol

7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition

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50 Configuration software identifies agent capabilities by checking the 66MHZ_CAPABLE bit in the Status register. This includes both the primary and secondary Status registers in a PCI-to-PCI bridge. This allows configuration software to detect a 33 MHz PCI agent on a 66 MHz PCI bus or a 66 MHz PCI agent on a

33 MHz PCI bus and issue a warning to the user describing the situation.

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7.5.2. Latency

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7.6. Electrical Specification

7.6.1. Overview

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51The bus 66MHZ_CAPABLE status bit is located in a bridge’s Status registers.

52This condition may cause the configuration software to generate a warning to the user stating that the card is installed in an inappropriate socket and should be relocated.

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7.6.2. Transition Roadmap to 66 MHz PCI

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7.6.3. Signaling Environment

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NOTES:

1.In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending upon whether the clock frequency is above 33 MHz.

a.Device operational parameters at frequencies at or under 33 MHz will conform to the specifications in Chapter 4. The clock frequency may be changed at any time during the operation of the system so long as the clock edges remain "clean" (monotonic) and the minimum cycle and high and low times are not violated. The clock may only be stopped in a low state. A variance on this specification is allowed for components designed for use on the system planar only. Refer to Section 4.2.3.1. for more information.

b.For clock frequencies between 33 MHz and 66 MHz, the clock frequency may not change except while RST# is asserted or when spread spectrum clocking (SSC) is used to reduce EMI emissions.

2.Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 7-2. Clock slew rate is measured by the slew rate circuit shown in Figure 7-7.

3.The minimum clock period must not be violated for any single clock cycle; i.e., accounting for all system jitter.

4.These values are duplicated from Section 4.2.3.1. and included here for comparison.

Implementation Note: Spread Spectrum Clocking (SSC)

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9.For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.

10.Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. Refer to Section 3.10., item 9 for additional details.

7.6.4.3.Measurement and Test Conditions

V_th

CLK

V_test

V_tl

T_val

OUTPUT

V_tfall

DELAY

T_val

Tri-State

OUTPUT

T_on

T_off

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V_th

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NOTES:

1.The test for the 3.3V environment is done with 0.1*Vcc of overdrive. Vmax specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values but must correlate results back to these parameters.

2.Vtrise and Vtfall are reference voltages for timing measurements only. Developers of 66 MHz PCI systems need to design buffers that launch enough energy into a 25 Ω transmission line so that correct input

levels are guaranteed after the first reflection.

3.Outputs will be characterized and measured at the package pin with the load shown in Figure 7-7. Input signal slew rate will be measured between 0.3Vcc and 0.6Vcc.

pin 1/2 in. max.

output buffer

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Vcc

25 Ω 10 pF

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