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Revision 2.2
6.4. Vital Product Data
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6.5. Device Drivers
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Revision 2.2
6.8. Message Signaled Interrupts
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6.8.1. Message Capability Structure
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Revision 2.2
Bits |
Field |
Description |
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6::4 |
Multiple Message |
System software writes to this field to indicate the |
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Enable |
number of allocated messages (equal to or less than |
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the number of requested messages). The number of |
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allocated messages is aligned to a power of two. If a |
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function requests four messages (indicated by a |
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Multiple Message Capable encoding of “010”), system |
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software can allocate either four, two, or one |
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message by writing a “010”, “001, or “000” to this |
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field, respectively. When MSI is enabled, a device will |
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be allocated at least 1 message. The encoding is |
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defined as: |
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Encoding |
# of messages allocated |
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000 |
1 |
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001 |
2 |
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010 |
4 |
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011 |
8 |
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100 |
16 |
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101 |
32 |
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110 |
Reserved |
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111 |
Reserved |
This field’s state after reset is “000”.
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This field is read/write. |
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3::1 |
Multiple Message |
System software reads this field to determine the |
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Capable |
number of requested messages. The number of |
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requested messages must be aligned to a power of |
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two (if a function requires three messages, it requests |
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four by initializing this field to “010”). The encoding is |
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defined as: |
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Encoding |
# of messages requested |
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000 |
1 |
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001 |
2 |
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010 |
4 |
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011 |
8 |
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100 |
16 |
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101 |
32 |
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110 |
Reserved |
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111 |
Reserved |
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This field is read/only. |
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Revision 2.2 |
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6.8.1.6. Message Data |
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Bits |
Field |
Description |
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15::00 |
Message Data |
System-specified message. |
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Each MSI function is allocated up to 32 unique |
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messages. |
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System architecture specifies the number of unique |
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messages supported by the system. |
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If the Message Enable bit (bit 0 of the Message |
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Control register) is set, the message data is driven |
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onto the lower word (AD[15::00]) of the memory write |
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transaction’s data phase. AD[31::16] are driven to |
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zero during the memory write transaction’s data |
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phase. C/BE[3::0]# are asserted during the data |
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phase of the memory write transaction. |
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The Multiple Message Enable field (bits 6-4 of the |
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Message Control register) defines the number of low |
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order message data bits the function is permitted to |
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modify to generate its system software allocated |
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messages. For example, a Multiple Message Enable |
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encoding of “010” indicates the function has been |
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allocated four messages and is permitted to modify |
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message data bits 1 and 0 (a function modifies the |
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lower message data bits to generate the allocated |
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number of messages). If the Multiple Message |
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Enable field is “000”, the function is not permitted to |
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modify the message data. |
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This field is read/write. |
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6.8.2. MSI Operation
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218
Revision 2.2
6.8.2.1. MSI Transaction Termination
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If the MSI write transaction results in a data parity error, the master that originated the MSI write transaction is required to assert SERR# (if bit 8 in the Command register is set) and to set the appropriated bits in the Status register (refer to Section 3.7.4.).
6.8.2.2. MSI Transaction Reception and Ordering Requirements
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