GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS

E.4.3 Example SIMD Floating-Point Emulation Implementation

The sample code listed below may be considered as being part of a user-level floating-point exception filter for the SSE/SSE2/SSE3 numeric instructions. It is assumed that the filter function is invoked by a low-level exception handler (reached via interrupt vector 19 when an unmasked floating-point exception occurs), and that it operates as explained in Section E.4.1, “Floating-Point Emulation.” The sample code does the emulation only for the SSE instructions for addition, subtraction, multiplication, and division. For this, it uses C code and x87 FPU operations. Operations corresponding to other SSE/SSE2/SSE3 numeric instructions can be emulated similarly. The example assumes that the emulation function receives a pointer to a data structure specifying a number of input parameters: the operation that caused the exception, a set of sub-operands (unpacked, of type float), the rounding mode (the precision is always single), exception masks (having the same relative bit positions as in the MXCSR but starting from bit 0 in an unsigned integer), and flush-to-zero and denormals-are-zeros indicators.

The output parameters are a floating-point result (of type float), the cause of the exception (identified by constants not explicitly defined below), and the exception status flags. The corresponding C definition is:

unsigned int operand1_uint32; //first operand value

unsigned int operand2_uint32; //second operand value (if any) float result_fval; // result value (if any)

unsigned int rounding_mode; //rounding mode

unsigned int exc_masks; //exception masks, in the order P,U,O,Z,D,I unsigned int exception_cause; //exception cause

unsigned int status_flag_inexact; //inexact status flag unsigned int status_flag_underflow; //underflow status flag unsigned int status_flag_overflow; //overflow status flag unsigned int status_flag_divide_by_zero;

//divide by zero status flag

unsigned int status_flag_denormal_operand;

//denormal operand status flag

unsigned int status_flag_invalid_operation;

//invalid operation status flag

unsigned int ftz; // flush-to-zero flag unsigned int daz; // denormals-are-zeros flag

} EXC_ENV;

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The arithmetic operations exemplified are emulated as follows:

1.If the denormals-are-zeros mode is enabled (the DAZ bit in MXCSR is set to 1), replace all the denormal inputs with zeroes of the same sign (the denormal flag is not affected by this change).

2.Perform the operation using x87 FPU instructions, with exceptions disabled, the original user rounding mode, and single precision. This reveals invalid, denormal, or divide-by-zero exceptions (if there are any) and stores the result in memory as a double precision value (whose exponent range is large enough to look like “unbounded” to the result of the single precision computation).

3.If no unmasked exceptions were detected, determine if the result is less than the smallest normal number (tiny) that can be represented in single precision format, or greater than the largest normal number that can be represented in single precision format (huge). If an unmasked overflow or underflow occurs, calculate the scaled result that will be handed to the user exception handler, as specified by IEEE Standard 754.

4.If no exception was raised, calculate the result with a “bounded” exponent. If the result is tiny, it requires denormalization (shifting the significand right while incrementing the exponent to bring it into the admissible range of [-126,+127] for single precision floating-point numbers).

The result obtained in step 2 cannot be used because it might incur a double rounding error (it was rounded to 24 bits in step 2, and might have to be rounded again in the denormalization process). To overcome this is, calculate the result as a double precision value, and store it to memory in single precision format.

Rounding first to 53 bits in the significand, and then to 24 never causes a double rounding error (exact properties exist that state when double-rounding error occurs, but for the elementary arithmetic operations, the rule of thumb is that if an infinitely precise result is rounded to 2p+1 bits and then again to p bits, the result is the same as when rounding directly to p bits, which means that no double-rounding error occurs).

5.If the result is inexact and the inexact exceptions are unmasked, the calculated result will be delivered to the user floating-point exception handler.

6.The flush-to-zero case is dealt with if the result is tiny.

7.The emulation function returns RAISE_EXCEPTION to the filter function if an exception has to be raised (the exception_cause field indicates the cause). Otherwise, the emulation function returns DO_NOT_ RAISE_EXCEPTION. In the first case, the result is provided by the user exception handler called by the filter function. In the second case, it is provided by the emulation function. The filter function has to collect all the partial results, and to assemble the scalar or packed result that is used if execution is to continue.

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Example E-1. SIMD Floating-Point Emulation

//masks for individual status word bits #define PRECISION_MASK 0x20

#define UNDERFLOW_MASK 0x10 #define OVERFLOW_MASK 0x08 #define ZERODIVIDE_MASK 0x04 #define DENORMAL_MASK 0x02 #define INVALID_MASK 0x01

//32-bit constants

//-Inf

//64-bit constants

static unsigned MIN_SINGLE_NORMAL_ARRAY [] = {0x00000000, 0x38100000}; #define MIN_SINGLE_NORMAL *(double *)MIN_SINGLE_NORMAL_ARRAY

// +1.0 * 2^-126

static unsigned MAX_SINGLE_NORMAL_ARRAY [] = {0x70000000, 0x47efffff}; #define MAX_SINGLE_NORMAL *(double *)MAX_SINGLE_NORMAL_ARRAY

// +1.1...1*2^127

static unsigned TWO_TO_192_ARRAY[] = {0x00000000, 0x4bf00000}; #define TWO_TO_192 *(double *)TWO_TO_192_ARRAY

// +1.0 * 2^192

static unsigned TWO_TO_M192_ARRAY[] = {0x00000000, 0x33f00000}; #define TWO_TO_M192 *(double *)TWO_TO_M192_ARRAY

//+1.0 * 2^-192

//auxiliary functions

static int isnanf (unsigned int ); // returns 1 if f is a NaN, and 0 otherwise static float quietf (unsigned int ); // converts a signaling NaN to a quiet

// NaN, and leaves a quiet NaN unchanged static unsigned int check_for_daz (unsigned int ); // converts denormals

//to zeros of the same sign;

//does not affect any status flags

//emulation of SSE and SSE2 instructions using

//C code and x87 FPU instructions

unsigned int

simd_fp_emulate (EXC_ENV *exc_env)

{

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int uiopd1; // first operand of the add, subtract, multiply, or divide int uiopd2; // second operand of the add, subtract, multiply, or divide float res; // result of the add, subtract, multiply, or divide

double dbl_res24; // result with 24-bit significand, but "unbounded" exponent

//(needed to check tininess, to provide a scaled result to

//an underflow/overflow trap handler, and in flush-to-zero mode) double dbl_res; // result in double precision format (needed to avoid a

//double rounding error when denormalizing)

unsigned int result_tiny; unsigned int result_huge; unsigned short int sw; // 16 bits unsigned short int cw; // 16 bits

//have to check first for faults (V, D, Z), and then for traps (O, U, I)

//initialize x87 FPU (floating-point exceptions are masked)

_asm { fninit;

}

result_tiny = 0; result_huge = 0;

switch (exc_env->operation) {

case ADDPS: case ADDSS: case SUBPS: case SUBSS: case MULPS: case MULSS: case DIVPS: case DIVSS:

uiopd1 = exc_env->operand1_uint32; // copy as unsigned int

//do not copy as float to avoid conversion

//of SNaN to QNaN by compiled code

uiopd2 = exc_env->operand2_uint32;

//do not copy as float to avoid conversion of SNaN

//to QNaN by compiled code

uiopd1 = check_for_daz (uiopd1); // operand1 = +0.0 * operand1 if it is // denormal and DAZ=1

uiopd2 = check_for_daz (uiopd2); // operand2 = +0.0 * operand2 if it is

//denormal and DAZ=1

//execute the operation and check whether the invalid, denormal, or

//divide by zero flags are set and the respective exceptions enabled

//set control word with rounding mode set to exc_env->rounding_mode,

//single precision, and all exceptions disabled

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switch (exc_env->rounding_mode) { case ROUND_TO_NEAREST:

cw = 0x003f; // round to nearest, single precision, exceptions masked break;

case ROUND_DOWN:

cw = 0x043f; // round down, single precision, exceptions masked break;

case ROUND_UP:

cw = 0x083f; // round up, single precision, exceptions masked break;

case ROUND_TO_ZERO:

cw = 0x0c3f; // round to zero, single precision, exceptions masked break;

default:

;

}

__asm {

fldcw WORD PTR cw;

}

//compute result and round to the destination precision, with

//"unbounded" exponent (first IEEE rounding)

switch (exc_env->operation) {

case ADDPS: case ADDSS:

// perform the addition __asm {

fnclex;

// load input operands

fld DWORD PTR uiopd1; // may set denormal or invalid status flags fld DWORD PTR uiopd2; // may set denormal or invalid status flags faddp st(1), st(0); // may set inexact or invalid status flags

// store result

fstp QWORD PTR dbl_res24; // exact

}

break;

case SUBPS: case SUBSS:

// perform the subtraction __asm {

fnclex;

// load input operands

fld DWORD PTR uiopd1; // may set denormal or invalid status flags fld DWORD PTR uiopd2; // may set denormal or invalid status flags fsubp st(1), st(0); // may set the inexact or invalid status flags

// store result

fstp QWORD PTR dbl_res24; // exact

}

break;

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case MULPS: case MULSS:

// perform the multiplication __asm {

fnclex;

// load input operands

fld DWORD PTR uiopd1; // may set denormal or invalid status flags fld DWORD PTR uiopd2; // may set denormal or invalid status flags fmulp st(1), st(0); // may set inexact or invalid status flags

// store result

fstp QWORD PTR dbl_res24; // exact

}

break;

case DIVPS: case DIVSS:

// perform the division __asm {

fnclex;

// load input operands

fld DWORD PTR uiopd1; // may set denormal or invalid status flags fld DWORD PTR uiopd2; // may set denormal or invalid status flags fdivp st(1), st(0); // may set the inexact, divide by zero, or

// invalid status flags

// store result

fstp QWORD PTR dbl_res24; // exact

}

break;

default:

; // will never occur

}

// read status word __asm {

fstsw WORD PTR sw;

}

if (sw & ZERODIVIDE_MASK)

sw = sw & ~DENORMAL_MASK; // clear D flag for (denormal / 0)

// if invalid flag is set, and invalid exceptions are enabled, take trap if (!(exc_env->exc_masks & INVALID_MASK) && (sw & INVALID_MASK)) {

exc_env->status_flag_invalid_operation = 1; exc_env->exception_cause = INVALID_OPERATION; return (RAISE_EXCEPTION);

}

// checking for NaN operands has priority over denormal exceptions;

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//also fix for the SSE and SSE2

//differences in treating two NaN inputs between the

//instructions and other IA-32 instructions

if (isnanf (uiopd1) || isnanf (uiopd2)) {

if (isnanf (uiopd1) && isnanf (uiopd2)) exc_env->result_fval = quietf (uiopd1);

else

exc_env->result_fval = (float)dbl_res24; // exact

if (sw & INVALID_MASK) exc_env->status_flag_invalid_operation = 1; return (DO_NOT_RAISE_EXCEPTION);

}

//if denormal flag set, and denormal exceptions are enabled, take trap if (!(exc_env->exc_masks & DENORMAL_MASK) && (sw & DENORMAL_MASK)) {

exc_env->status_flag_denormal_operand = 1; exc_env->exception_cause = DENORMAL_OPERAND; return (RAISE_EXCEPTION);

}

//if divide by zero flag set, and divide by zero exceptions are

//enabled, take trap (for divide only)

if (!(exc_env->exc_masks & ZERODIVIDE_MASK) && (sw & ZERODIVIDE_MASK)) { exc_env->status_flag_divide_by_zero = 1;

exc_env->exception_cause = DIVIDE_BY_ZERO; return (RAISE_EXCEPTION);

}

//done if the result is a NaN (QNaN Indefinite) res = (float)dbl_res24;

if (isnanf (*(unsigned int *)&res)) { exc_env->result_fval = res; // exact exc_env->status_flag_invalid_operation = 1; return (DO_NOT_RAISE_EXCEPTION);

}

//dbl_res24 is not a NaN at this point

if (sw & DENORMAL_MASK) exc_env->status_flag_denormal_operand = 1;

// Note: (dbl_res24 == 0.0 && sw & PRECISION_MASK) cannot occur if (-MIN_SINGLE_NORMAL < dbl_res24 && dbl_res24 < 0.0 ||

0.0 < dbl_res24 && dbl_res24 < MIN_SINGLE_NORMAL) { result_tiny = 1;

}

// check if the result is huge

if (NEGINFF < dbl_res24 && dbl_res24 < -MAX_SINGLE_NORMAL || MAX_SINGLE_NORMAL < dbl_res24 && dbl_res24 < POSINFF) {

result_huge = 1;

}

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//at this point, there are no enabled I,D, or Z exceptions

//to take; the instr.

//might lead to an enabled underflow, enabled underflow and inexact,

//enabled overflow, enabled overflow and inexact, enabled inexact, or

//none of these; if there are no U or O enabled exceptions, re-execute

//the instruction using IA-32 double precision format, and the

//user's rounding mode; exceptions must have

//been disabled before calling

//this function; an inexact exception may be reported on the 53-bit

//fsubp, fmulp, or on both the 53-bit and 24-bit conversions, while an

//overflow or underflow (with traps disabled) may be reported on the

//conversion from dbl_res to res

//check whether there is an underflow, overflow,

//or inexact trap to be taken

//if the underflow traps are enabled and the result is

//tiny, take underflow trap

if (!(exc_env->exc_masks & UNDERFLOW_MASK) && result_tiny) { dbl_res24 = TWO_TO_192 * dbl_res24; // exact exc_env->status_flag_underflow = 1; exc_env->exception_cause = UNDERFLOW;

exc_env->result_fval = (float)dbl_res24; // exact

if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1; return (RAISE_EXCEPTION);

}

//if overflow traps are enabled and the result is huge, take

//overflow trap

if (!(exc_env->exc_masks & OVERFLOW_MASK) && result_huge) { dbl_res24 = TWO_TO_M192 * dbl_res24; // exact exc_env->status_flag_overflow = 1; exc_env->exception_cause = OVERFLOW;

exc_env->result_fval = (float)dbl_res24; // exact

if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1; return (RAISE_EXCEPTION);

}

//set control word with rounding mode set to exc_env->rounding_mode,

//double precision, and all exceptions disabled

cw = cw | 0x0200; // set precision to double __asm {

fldcw WORD PTR cw;

}

switch (exc_env->operation) {

case ADDPS: case ADDSS:

// perform the addition __asm {

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case MULPS: case MULSS:

// perform the multiplication __asm {

default:

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; // will never occur

}

//calculate result for the case an inexact trap has to be taken, or

//when no trap occurs (second IEEE rounding)

res = (float)dbl_res;

//may set P, U or O; may also involve denormalizing the result

//read status word

__asm {

fstsw WORD PTR sw;

}

// if inexact traps are enabled and result is inexact, take inexact trap if (!(exc_env->exc_masks & PRECISION_MASK) &&

((sw & PRECISION_MASK) || (exc_env->ftz && result_tiny))) { exc_env->status_flag_inexact = 1;

exc_env->exception_cause = INEXACT; if (result_tiny) {

exc_env->status_flag_underflow = 1;

//if ftz = 1 and result is tiny, result = 0.0

//(no need to check for underflow traps disabled: result tiny and

//underflow traps enabled would have caused taking an underflow

//trap above)

if (exc_env->ftz) {

}

}

if (result_huge) exc_env->status_flag_overflow = 1; exc_env->result_fval = res;

return (RAISE_EXCEPTION);

}

//if it got here, then there is no trap to be taken; the following must

//hold: ((the MXCSR U exceptions are disabled or

//

//the MXCSR underflow exceptions are enabled and the underflow flag is

//clear and (the inexact flag is set or the inexact flag is clear and

//the 24-bit result with unbounded exponent is not tiny)))

//and (the MXCSR overflow traps are disabled or the overflow flag is

//clear) and (the MXCSR inexact traps are disabled or the inexact flag

//is clear)

//

//in this case, the result has to be delivered (the status flags are

//sticky, so they are all set correctly already)

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// read status word to see if result is inexact __asm {

fstsw WORD PTR sw;

//if ftz = 1, and result is tiny (underflow traps must be disabled),

//result = 0.0

if (exc_env->ftz && result_tiny) { if (res > 0.0)

res = ZEROF;

else if (res < 0.0) res = NZEROF;

// else leave res unchanged

exc_env->status_flag_inexact = 1; exc_env->status_flag_underflow = 1;

}

exc_env->result_fval = res;

if (sw & ZERODIVIDE_MASK) exc_env->status_flag_divide_by_zero = 1; if (sw & DENORMAL_MASK) exc_env->status_flag_denormal= 1;

if (sw & INVALID_MASK) exc_env->status_flag_invalid_operation = 1; return (DO_NOT_RAISE_EXCEPTION);

break;

case CMPPS: case CMPSS:

...

break;

case COMISS: case UCOMISS:

...

break;

case CVTPI2PS: case CVTSI2SS:

...

break;

case CVTPS2PI:

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case CVTSS2SI: case CVTTPS2PI: case CVTTSS2SI:

...

break;

case MAXPS: case MAXSS: case MINPS: case MINSS:

...

break;

case SQRTPS: case SQRTSS:

...

break;

...

case UNSPEC:

...

break;

default:

...

}

}

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