PROGRAMMING WITH SSE3 AND SUPPLEMENTAL SSE3

12.7.2Checking for SSSE3 Support

Before an application attempts to use the SIMD subset of SSSE3 extensions, the application should follow the steps illustrated in Section 11.6.2, “Checking for SSE/SSE2 Support.” Next, use the additional step provided below:

•Check that the processor supports the SIMD and x87 SSSE3 extensions (if CPUID.01H:ECX.SSSE3[bit 9] = 1). See Example 12-3 for a code example.

Example 12-3. Verifying SSSE3 Support

boolean SSSE3_SIMD_works = TRUE; try {

Issue_SSSE3_SIMD_Instructions(); // Use PHADDD

}

except (UNWIND)

{

// if we get here, SSSE3 not available SSSE3_SIMD_works = FALSE;

}

12.8SSE3/SSSE3 EXCEPTIONS

SSE3/SSSE3 instructions can generate the same type of memory-access and nonnumeric exceptions as other Intel 64 or IA-32 instructions. Existing exception handlers generally handle these exceptions without code modification.

FISTTP can generate floating-point exceptions. Some SSE3 instructions can also generate SIMD floating-point exceptions.

SSE3 additions and changes are noted in the following sections. See also: Section 11.5, “SSE, SSE2, and SSE3 Exceptions”

12.8.1Device Not Available (DNA) Exceptions

SSE3/SSSE3 will cause a DNA Exception (#NM) if the processor attempts to execute an SSE3 instruction while CR0.TS[bit 3] = 1. If CPUID.01H:ECX.SSE3[bit 0] = 0, execution of an SSE3 extension will cause an invalid opcode fault regardless of the state of CR0.TS[bit 3].

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12.8.2Numeric Error flag and IGNNE#

Most SSE3 instructions ignore CR0.NE[bit 5] (treats it as if it were always set) and the IGNNE# pin. With one exception, all use the vector 19 software exception for error reporting. The exception is FISTTP; it behaves like other x87-FP instructions.

SSSE3 instructions ignore CR0.NE[bit 5] (treats it as if it were always set) and the IGNNE# pin. SSSE3 instructions do not cause floating-point errors.

12.8.3Emulation

Used to emulate x87 floating-point instructions, CR0.EM[bit 2] cannot be used for emulation of SSE3/SSSE3. If an SSE3/SSSE3 instruction executes with CR0.EM[bit 2] set, an invalid opcode exception (INT 6) is generated instead of a device not available exception (INT 7).

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CHAPTER 13

INPUT/OUTPUT

In addition to transferring data to and from external memory, IA-32 processors can also transfer data to and from input/output ports (I/O ports). I/O ports are created in system hardware by circuity that decodes the control, data, and address pins on the processor. These I/O ports are then configured to communicate with peripheral devices. An I/O port can be an input port, an output port, or a bidirectional port. Some I/O ports are used for transmitting data, such as to and from the transmit and receive registers, respectively, of a serial interface device. Other I/O ports are used to control peripheral devices, such as the control registers of a disk controller.

This chapter describes the processor’s I/O architecture. The topics discussed include:

13.1I/O PORT ADDRESSING

The processor permits applications to access I/O ports in either of two ways:

Accessing I/O ports through the I/O address space is handled through a set of I/O instructions and a special I/O protection mechanism. Accessing I/O ports through memory-mapped I/O is handled with the processors general-purpose move and string instructions, with protection provided through segmentation or paging. I/O ports can be mapped so that they appear in the I/O address space or the physicalmemory address space (memory mapped I/O) or both.

One benefit of using the I/O address space is that writes to I/O ports are guaranteed to be completed before the next instruction in the instruction stream is executed. Thus, I/O writes to control system hardware cause the hardware to be set to its new state before any other instructions are executed. See Section 13.6, “Ordering I/O,” for more information on serializing of I/O operations.

13.2I/O PORT HARDWARE

From a hardware point of view, I/O addressing is handled through the processor’s address lines. For the P6 family, Pentium 4, and Intel Xeon processors, the request command lines signal whether the address lines are being driven with a memory address or an I/O address; for Pentium processors and earlier IA-32 processors, the M/IO# pin indicates a memory address (1) or an I/O address (0). When the separate

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