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МИРЭА - Российский технологический университет

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Радиоприемные устройства

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Микроконтроллер Motorola 68HC11.pdf

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Table A-7 Expansion Bus Timing

		VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH

	Num	Characteristic		Symbol	1.0 MHz		2.0 MHz		3.0 MHz			Unit

					Min	Max	Min	Max	Min	Max

		Frequency of Operation (E-Clock Frequency)		fo	dc	1.0	dc	2.0	dc	3.0		MHz
	1	Cycle Time		tcyc	1000	—	500	—	333	—	ns
	2	Pulse Width, E Low		PWEL	477	—	227	—	146	—	ns
		PWEL = 1/2 tcyc –23 ns	(Note 1)
	3	Pulse Width, E High		PWEH	472	—	222	—	141	—	ns
		PWEH = 1/2 tcyc –28 ns	(Note 1)
	4a	E and AS Rise Time		tr	—	20	—	20	—	20		ns
	4b	E and AS Fall Time		tf	—	20	—	20	—	15
	9	Address Hold Time		tAH	95.5	—	33	—	26	—	ns
		tAH = 1/8 tcyc –29.5 ns	(Note 1, 2a)
	12	Nonmultiplexed Address Valid Time to E Rise		tAV	281.5	—	94	—	54	—	ns
A		tAV = PWEL –(tASD + 80 ns)	(Note 1, 2a)
	17	Read Data Setup Time		tDSR	30	—	30	—	30	—	ns
	18	Read Data Hold Time (Max = tMAD)		tDHR	0	145.5	0	83	0	51		ns
	19	Write Data Delay Time		tDDW	—	190.5	—	128		71	ns
		tDDW = 1/8 tcyc + 65.5 ns	(Note 1, 2a)
	21	Write Data Hold Time		tDHW	95.5	—	33	—	26	—	ns
		tDHW = 1/8 tcyc –29.5 ns	(Note 1, 2a)
	22	Multiplexed Address Valid Time to E Rise		tAVM	271.5	—	84	—	54	—	ns
		tAVM = PWEL –(tASD + 90 ns)	(Note 1, 2a)
	24	Multiplexed Address Valid Time to AS Fall		tASL	151	—	26	—	13	—	ns
		tASL = PWASH –70 ns	(Note 1)
	25	Multiplexed Address Hold Time		tAHL	95.5	—	33	—	31	—	ns
		tAHL = 1/8 tcyc –29.5 ns	(Note 1, 2b)
	26	Delay Time, E to AS Rise		tASD	115.5	—	53	—	31	—	ns
		tASD = 1/8 tcyc –9.5 ns	(Note 1, 2a)
	27	Pulse Width, AS High		PWASH	221	—	96	—	63	—	ns
		PWASH = 1/4 tcyc –29 ns	(Note 1)
	28	Delay Time, AS to E Rise		tASED	115.5	—	53	—	31	—	ns
		tASED = 1/8 tcyc –9.5 ns	(Note 1, 2b)
	29	MPU Address Access Time	(Note 2a)	tACCA	744.5	—	307	—	196	—	ns
		tACCA = tcyc –(PWEL–tAVM) –tDSR–tf
	35	MPU Access Time		tACCE	—	442	—	192		111	ns
		tACCE = PWEH –tDSR
	36	Multiplexed Address Delay		tMAD	145.5	—	83	—	51	—	ns
		(Previous Cycle MPU Read)
		tMAD = tASD + 30 ns	(Note 1, 2a)

1.Formula only for dc to 2 MHz.

2.Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place of 1/8 tcyc in the above formulas, where applicable:

(a)(1–DC) × 1/4 tcyc

(b)DC × 1/4 tcyc

Where:

DC is the decimal value of duty cycle percentage (high time).

3. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.

MOTOROLA	ELECTRICAL CHARACTERISTICS	M68HC11 E SERIES
A-18		TECHNICAL DATA

Table A-7a Expansion Bus Timing (MC68L11E9)

VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH

Num	Characteristic		Symbol	1.0 MHz		2.0 MHz		Unit

				Min	Max	Min	Max

	Frequency of Operation (E-Clock Frequency)		fo	dc	1.0	dc	2.0	MHz
1	Cycle Time		tcyc	1000	—	500	—	ns
2	Pulse Width, E Low		PWEL	475	—	225	—	ns
	PWEL = 1/2 tcyc –25 ns
3	Pulse Width, E High		PWEH	470	—	220	—	ns
	PWEH = 1/2 tcyc –30 ns
4A	E and AS Rise Time		tr	—	25	—	25	ns
4B	E and AS Fall Time		tf	—	25	—	25	ns
9	Address Hold Time		tAH	95	—	33	—	ns
	tAH = 1/8 tcyc –30 ns	(Note 1a)
12	Nonmultiplexed Address Valid Time to E Rise		tAV	275	—	88	—	ns
	tAV = PWEL –(tASD + 80 ns)	(Note 1a)							A
17	Read Data Setup Time		tDSR	30	—	30	—	ns
18	Read Data Hold Time (Max = tMAD)		tDHR	0	150	0	88	ns
19	Write Data Delay Time		tDDW	—	195	—	133	ns
	tDDW = 1/8 tcyc + 70 ns	(Note 1a)
21	Write Data Hold Time		tDHW	95	—	33	—	ns
	tDHW = 1/8 tcyc –30 ns	(Note 1a)
22	Multiplexed Address Valid Time to E Rise		tAVM	265	—	78	—	ns
	tAVM = PWEL –(tASD + 90 ns)	(Note 1a)
24	Multiplexed Address Valid Time to AS Fall		tASL	150	—	25	—	ns
	tASL = PWASH –70 ns
25	Multiplexed Address Hold Time		tAHL	95	—	33	—	ns
	tAHL = 1/8 tcyc –30 ns	(Note 1b)
26	Delay Time, E to AS Rise		tASD	120	—	58	—	ns
	tASD = 1/8 tcyc –5 ns	(Note 1a)
27	Pulse Width, AS High		PWASH	220	—	95	—	ns
	PWASH = 1/4 tcyc –30 ns
28	Delay Time, AS to E Rise		tASED	120	—	58	—	ns
	tASED = 1/8 tcyc –5 ns	(Note 1b)
29	MPU Address Access Time	(Note 1a)	tACCA	735	—	298	—	ns
	tACCA = tcyc –(PWEL–tAVM) –tDSR–tf
35	MPU Access Time		tACCE	—	440	—	190	ns
	tACCE = PWEH –tDSR
36	Multiplexed Address Delay		tMAD	150	—	88	—	ns
	(Previous Cycle MPU Read)
	tMAD = tASD + 30 ns	(Note 1a)

NOTES:

1.Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place of 1/8 tcyc in the above formulas, where applicable:

(a)(1–DC) × 1/4 tcyc

(b)DC × 1/4 tcyc

Where:

DC is the decimal value of duty cycle percentage (high time).

2. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.

M68HC11 E SERIES	ELECTRICAL CHARACTERISTICS	MOTOROLA
TECHNICAL DATA		A-19

			1
		2		3	4B
	E
			4A
		12			9
	R/W, ADDRESS
	(NON-MUX)
	36	22		35	17
	36		29		18
			29		18
	READ	ADDRESS			DATA
	ADDRESS/DATA		19		21
	(MULTIPLEXED)		19		21
	(MULTIPLEXED)
	WRITE	ADDRESS			DATA
A		25
	4A	24	4B
	AS
	26	27	28

NOTE: Measurement points shown are 20% and 70% of VDD.

MUX BUS TIM

Figure A-14 Multiplexed Expansion Bus Timing Diagram

MOTOROLA	ELECTRICAL CHARACTERISTICS	M68HC11 E SERIES
A-20		TECHNICAL DATA

Table A-8 Serial Peripheral Interface Timing

	VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH

Num	Characteristic		Symbol	2.0 MHz		3.0 MHz		Unit

				Min	Max	Min	Max

	Operating Frequency			dc	0.5	dc	0.5	fop
	Master		fop(m)	dc	0.5	dc	0.5	fop
	Slave		fop(s)	dc	2.0	dc	3.0	MHz
1	Cycle Time			2.0	—	2.0	—	tcyc
	Master		tcyc(m)	2.0	—	2.0	—	tcyc
	Slave		tcyc(s)	500	—	333	—	ns
2	Enable Lead Time			—	—	—	—	ns
	Master (Note 2)		tlead(m)	—	—	—	—	ns
	Slave		tlead(s)	250	—	240	—	ns
3	Enable Lag Time			—	—	—	—	ns
	Master (Note 2)		tlag(m)	—	—	—	—	ns
	Slave		tlag(s)	250	—	240	—	ns
4	Clock (SCK) High Time			340	—	227	—	ns	A
	Master		tw(SCKH)m	340	—	227	—	ns
	Slave		tw(SCKH)s	190	—	127	—	ns
5	Clock (SCK) Low Time			340	—	227	—	ns
	Master		tw(SCKL)m	340	—	227	—	ns
	Slave		tw(SCKL)s	190	—	127	—	ns
6	Data Setup Time (Inputs)			100	—	100	—	ns
	Master		tsu(m)	100	—	100	—	ns
	Slave		tsu(s)	100	—	100	—	ns
7	Data Hold Time (Inputs)			100	—	100	—	ns
	Master		th(m)	100	—	100	—	ns
	Slave		th(s)	100	—	100	—	ns
8	Access Time (Time to Data Active from
	High-Impedance State)			0	120	0	120	ns
	Slave		ta	0	120	0	120	ns
9	Disable Time (Hold Time to High-Impedance State)			—	240	—	167	ns
	Slave		tdis	—	240	—	167	ns
10	Data Valid (After Enable Edge) (Note 3)		tv(s)	—	240	—	167	ns
11	Data Hold Time (Outputs) (After Enable Edge)		tho	0	—	0	—	ns
12	Rise Time (20% VDD to 70% VDD, CL = 200 pF)		trm
	SPI Outputs (SCK, MOSI, and MISO)		trm	—	100	—	100	ns
	SPI Inputs (SCK, MOSI, MISO, and	SS)	trs	—	2.0	—	2.0	s
13	Fall Time (70% VDD to 20% VDD, CL = 200 pF)		tfm
	SPI Outputs (SCK, MOSI, and MISO)		tfm	—	100	—	100	ns
	SPI Inputs (SCK, MOSI, MISO, and	SS)	tfs	—	2.0	—	2.0	s

1.All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.

2.Signal production depends on software.

3.Assumes 200 pF load on SCK, MOSI, and MISO pins.

M68HC11 E SERIES	ELECTRICAL CHARACTERISTICS	MOTOROLA
TECHNICAL DATA		A-21

Table A-8a Serial Peripheral Interface Timing (MC68L11E9)

	Num	Characteristic		Symbol	1.0 MHz		2.0 MHz		Unit

					Min	Max	Min	Max

		Operating Frequency			dc	0.5	dc	0.5	fop
		Master		fop(m)	dc	0.5	dc	0.5	fop
		Slave		fop(s)	dc	1.0	dc	2.0	MHz
	1	Cycle Time			2.0	—	2.0	—	tcyc
		Master		tcyc(m)	2.0	—	2.0	—	tcyc
		Slave		tcyc(s)	1000	—	500	—	ns
	2	Enable Lead Time			—	—	—	—	ns
		Master (Note 2)		tlead(m)	—	—	—	—	ns
		Slave		tlead(s)	500	—	250	—	ns
	3	Enable Lag Time			—	—	—	—	ns
		Master (Note 2)		tlag(m)	—	—	—	—	ns
		Slave		tlag(s)	500	—	250	—	ns
	4	Clock (SCK) High Time			680	—	340	—	ns
		Master		tw(SCKH)m	680	—	340	—	ns
A		Slave		tw(SCKH)s	380	—	190	—	ns
	5	Clock (SCK) Low Time			680	—	340	—	ns
		Master		tw(SCKL)m	680	—	340	—	ns
		Slave		tw(SCKL)s	380	—	190	—	ns
	6	Data Setup Time (Inputs)			100	—	100	—	ns
	6	Master		tsu(m)	100	—	100	—	ns
		Slave		tsu(s)	100	—	100	—	ns
	7	Data Hold Time (Inputs)			100	—	100	—	ns
		Master		th(m)	100	—	100	—	ns
		Slave		th(s)	100	—	100	—	ns
	8	Access Time
		(Time to Data Active from High-Impedance			0	120	0	120	ns
		State)		ta	0	120	0	120	ns
		Slave

	9	Disable Time
		(Hold Time to High-Impedance State)			—	240	—	240	ns
		Slave		tdis	—	240	—	240	ns
	10	Data Valid (After Enable Edge) (Note 3)		tv(s)	—	240	—	240	ns
	11	Data Hold Time (Outputs) (After Enable Edge)		tho	0	—	0	—	ns
	12	Rise Time (20% VDD to 70% VDD, CL = 200 pF)		trm
		SPI Outputs (SCK, MOSI, and MISO)		trm	—	100	—	100	ns
		SPI Inputs (SCK, MOSI, MISO, and	SS)	trs	—	2.0	—	2.0	s
	13	Fall Time (70% VDD to 20% VDD, CL = 200 pF)		tfm
		SPI Outputs (SCK, MOSI, and MISO)		tfm	—	100	—	100	ns
		SPI Inputs (SCK, MOSI, MISO, and	SS)	tfs	—	2.0	—	2.0	s

NOTES:

1.All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.

2.Signal production depends on software.

3.Assumes 100 pF load on all SPI pins.

MOTOROLA	ELECTRICAL CHARACTERISTICS	M68HC11 E SERIES
A-22		TECHNICAL DATA

SS	SS is held high on master.
(INPUT)	SS is held high on master.
(INPUT)
	1	13	12

SCK (CPOL = 0)	SEE		5
SCK (CPOL = 0)	SEE
(OUTPUT)	NOTE	4
		4		13	12
		5		13	12
SCK (CPOL = 1)	SEE	5
SCK (CPOL = 1)	SEE
(OUTPUT)	NOTE		4
	6	7	4
	6	7
MISO		MSB IN		BIT 6 - - - -1	LSB IN
(INPUT)		MSB IN		BIT 6 - - - -1	LSB IN
(INPUT)
	10 (ref)		11	10	11 (ref)
MOSI	MASTER MSB OUT			BIT 6 - - - -1	MASTER LSB OUT
(OUTPUT)	MASTER MSB OUT			BIT 6 - - - -1	MASTER LSB OUT
(OUTPUT)
	13				12
NOTE: This first clock edge is generated internally but is not seen at the SCK pin.					SPI MASTER CPHA0 TIM
					SPI MASTER CPHA0 TIM

a) SPI Master Timing (CPHA = 0)

SS	SS is held high on master.
(INPUT)	SS is held high on master.
(INPUT)
	1		13	12
SCK (CPOL = 0)	5
SCK (CPOL = 0)					SEE
(OUTPUT)	4				NOTE
	4
	5			13
SCK (CPOL = 1)	5				SEE
SCK (CPOL = 1)					SEE
(OUTPUT)	4				NOTE
	4	12		6	7
		12		6	7
MISO	MSB IN		BIT 6 - - - -1		LSB IN
(INPUT)	MSB IN		BIT 6 - - - -1		LSB IN
(INPUT)
	10 (ref)	11	10		11 (ref)

MOSI

MASTER MSB OUT

BIT 6 - - - -1

MASTER LSB OUT

(OUTPUT)

NOTE: This last clock edge is generated internally but is not seen at the SCK pin.

SPI MASTER CPHA1 TIM

b) SPI Master Timing (CPHA = 1) Figure A-15 SPI Timing Diagram (1 of 2)

M68HC11 E SERIES	ELECTRICAL CHARACTERISTICS	MOTOROLA
TECHNICAL DATA		A-23

SS (INPUT)

SCK (CPOL = 0) (INPUT)

SCK (CPOL = 1) (INPUT)

MISO (OUTPUT)

MOSI (INPUT)

		1
	2	4
	2	5
		5
	8
	SLAVE	MSB OUT
	6	7

MSB IN

5	13	12	3
5
4	12	13	9
	12	13	9
	BIT 6 - - - -1	SLAVE LSB OUT	SEE
	BIT 6 - - - -1	SLAVE LSB OUT	NOTE
			NOTE
10	11	11
	BIT 6 - - - -1	LSB IN

NOTE: Not defined but normally MSB of character just received.

SPI SLAVE CPHA0 TIM

a) SPI Slave Timing (CPHA = 0)

SS (INPUT)

SCK (CPOL = 0) (INPUT)

SCK (CPOL = 1) (INPUT)

MISO (OUTPUT)

SEE

NOTE

MOSI (INPUT)

1	5
	5
10	4
10
SLAVE	MSB OUT
6	7

MSB IN

	12	13
4			3
5			3
5
	13	12	9
BIT 6 - - - -1		SLAVE LSB OUT
10	11
BIT 6 - - - -1		LSB IN

NOTE: Not defined but normally LSB of character previously transmitted.

SPI SLAVE CPHA1 TIM

b) SPI Slave Timing (CPHA = 1) Figure A-15 SPI Timing Diagram (2 of 2)

MOTOROLA	ELECTRICAL CHARACTERISTICS	M68HC11 E SERIES
A-24		TECHNICAL DATA

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