Table A-4 Control Timing
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VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH |
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Characteristic |
Symbol |
1.0 MHz |
2.0 MHz |
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3.0 MHz |
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Unit |
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Min |
Max |
Min |
Max |
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Min |
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Max |
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Frequency of Operation |
fo |
dc |
1.0 |
dc |
2.0 |
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dc |
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3.0 |
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MHz |
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E-Clock Period |
tcyc |
1000 |
— |
500 |
— |
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333 |
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— |
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ns |
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Crystal Frequency |
fXTAL |
— |
4.0 |
— |
8.0 |
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— 12.0 |
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MHz |
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External Oscillator Frequency |
4 fo |
dc |
4.0 |
dc |
8.0 |
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dc |
12.0 |
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MHz |
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Processor Control Setup Time |
tPCSU |
300 |
— |
175 |
— |
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133 |
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— |
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ns |
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tPCSU = 1/4 tcyc + 50 ns |
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Reset Input Pulse Width |
PWRSTL |
8 |
— |
8 |
— |
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8 |
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— |
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tcyc |
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To Guarantee External Reset Vector |
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Minimum Input Time (Can Be Preempted by Internal Reset) |
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1 |
— |
1 |
— |
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1 |
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— |
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Mode Programming Setup Time |
tMPS |
2 |
— |
2 |
— |
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2 |
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— |
t |
cyc |
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Mode Programming Hold Time |
tMPH |
10 |
— |
10 |
— |
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10 |
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— |
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ns |
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Interrupt Pulse Width, |
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Edge-Sensitive Mode |
PWIRQ |
1020 |
— |
520 |
— |
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353 |
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— |
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ns |
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IRQ |
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PWIRQ = tcyc + 20 ns |
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A |
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Wait Recovery Start-up Time |
tWRS |
— |
4 |
— |
4 |
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4 |
t |
cyc |
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Timer Pulse Width Input Capture Pulse Accumulator Input |
PWTIM |
1020 |
— |
520 |
— |
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353 |
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— |
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ns |
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PWTIM = tcyc + 20 ns |
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NOTES: |
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1.RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to SECTION 5 RESETS AND INTERRUPTS for further detail.
2.All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
Table A-4a Control Timing (MC68L11E9)
VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH
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Characteristic |
Symbol |
1.0 MHz |
2.0 MHz |
Unit |
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Min |
Max |
Min |
Max |
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Frequency of Operation |
fo |
dc |
1.0 |
dc |
2.0 |
MHz |
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E-Clock Period |
tcyc |
1000 |
— |
500 |
— |
ns |
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Crystal Frequency |
fXTAL |
— |
4.0 |
— |
8.0 |
MHz |
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External Oscillator Frequency |
4 fo |
dc |
4.0 |
dc |
8.0 |
MHz |
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Processor Control Setup Time |
tPCSU |
325 |
— |
200 |
— |
ns |
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tPCSU = 1/4 tcyc + 75 ns |
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Reset Input Pulse Width |
PWRSTL |
8 |
— |
8 |
— |
tcyc |
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To Guarantee External Reset Vector |
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Minimum Input Time (Can Be Preempted by Internal Reset) |
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1 |
— |
1 |
— |
tcyc |
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Mode Programming Setup Time |
tMPS |
2 |
— |
2 |
— |
t cyc |
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Mode Programming Hold Time |
tMPH |
10 |
— |
10 |
— |
ns |
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Interrupt Pulse Width, |
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Edge-Sensitive Mode |
PWIRQ |
1020 |
— |
520 |
— |
ns |
IRQ |
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PWIRQ = tcyc + 20 ns |
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Wait Recovery Start-up Time |
tWRS |
— |
4 |
— |
4 |
t cyc |
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Timer Pulse Width, Input Capture Pulse Accumulator Input |
PWTIM |
1020 |
— |
520 |
— |
ns |
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PWTIM = tcyc + 20 ns |
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NOTES: |
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1.RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to SECTION 5 RESETS AND INTERRUPTS for further detail.
2.All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
M68HC11 E SERIES |
ELECTRICAL CHARACTERISTICS |
MOTOROLA |
TECHNICAL DATA |
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A-5 |
PA[2:0]1
PA[2:0]2
PA71,3
PWTIM 
PA72,3
NOTES:
1.Rising edge sensitive input
2.Falling edge sensitive input
3.Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
Figure A-2 Timer Inputs
A
MOTOROLA |
ELECTRICAL CHARACTERISTICS |
A-6
TIMER INPUTS TIM
M68HC11 E SERIES
TECHNICAL DATA
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NEW PC |
RESET TIM |
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FFFF |
POR EXT |
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FFFE |
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MPH |
FFFE |
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t |
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FFFE |
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MPS |
FFFE |
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t |
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RSTL |
FFFE |
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PW |
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PCSU |
NEW PC |
t |
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FFFF |
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FFFE |
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FFFE |
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FFFE |
CYC |
FFFE |
4064 t |
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V |
EXTAL |
E |
RESET |
MODBMODA, |
ADDRESS |
DD |
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A
Figure A-3 POR External Reset Timing Diagram
M68HC11 E SERIES |
ELECTRICAL CHARACTERISTICS |
MOTOROLA |
TECHNICAL DATA |
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A-7 |
8-A |
MOTOROLA |
CHARACTERISTICS ELECTRICAL |
Diagram Timing Recovery STOP 4-A Figure |
A
INTERNAL
CLOCKS
IRQ1
PWIRQ 
IRQ or XIRQ
tSTOPDELAY3
TIM RECOVERY STOP
E
ADDRESS4 |
STOP |
STOP |
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ADDR |
ADDR + 1 |
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ADDRESS5 |
STOP |
STOP |
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ADDR |
ADDR + 1 |
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NOTES:
1.Edge Sensitive IRQ pin (IRQE bit = 1)
2.Level sensitive IRQ pin (IRQE bit = 0)
3. tSTOPDELAY = 4064 tCYC if DLY bit = 1 or 4 tCYC if DLY = 0.
4.XIRQ with X bit in CCR = 1.
5.IRQ or (XIRQ with X bit in CCR = 0).
STOP
OPCODE
ADDR + 1
Resume program with instruction which follows the STOP instruction.
STOP |
STOP |
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FFF2 |
FFF3 |
NEW |
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SP…SP–7 |
SP – 8 |
SP – 8 |
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ADDR + 1 |
ADDR + 2 |
(FFF4) |
(FFF5) |
PC |
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DATA TECHNICAL |
SERIES E M68HC11 |
TECHNICAL |
E M68HC11 |
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DATA |
SERIES |
Figure |
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5-A |
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CHARACTERISTICS ELECTRICAL |
Timing Interrupt from Recovery WAIT |
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Diagram |
9-A |
MOTOROLA |
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E
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tPCSU |
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IRQ, |
XIRQ, |
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OR INTERNAL |
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INTERRUPTS |
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tWRS |
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NEW |
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ADDRESS |
WAIT |
WAIT |
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SP |
SP – 1 |
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SP – 8 |
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SP – 8 |
SP – 8 |
SP – 8 |
VECTOR |
VECTOR |
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SP – 2…SP – 8 |
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SP – 8…SP – 8 |
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ADDR |
ADDR + 1 |
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ADDR |
ADDR + 1 |
PC |
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PCL |
PCH, YL, YH, XL, XH, A, B, CCR |
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STACK REGISTERS
R/W
NOTE: RESET also causes recovery from WAIT.
TIM RECOVERY WAIT
A
10-A |
MOTOROLA |
CHARACTERISTICS ELECTRICAL |
Diagram Timing Interrupt 6-A Figure |
A
E
tPCSU
IRQ 1
PWIRQ 
IRQ 2, XIRQ,
OR INTERNAL
INTERRUPT
ADDRESS |
NEXT |
NEXT |
SP |
SP – 1 |
SP – 2 |
SP – 3 |
SP – 4 |
SP – 5 |
SP – 6 |
SP – 7 |
SP – 8 |
SP – 8 |
VECTOR |
VECTOR |
NEW |
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OPCODE |
OP + 1 |
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ADDR |
ADDR + 1 |
PC |
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DATA |
OP |
– – |
PCL |
PCH |
IYL |
IYH |
IXL |
IXH |
B |
A |
CCR |
– – |
VECT |
VECT |
OP |
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CODE |
MSB |
LSB |
CODE |
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R/W
NOTES:
1.Edge sensitive IRQ pin (IRQE bit = 1)
2.Level sensitive IRQ pin (IRQE bit = 0)
TIM INTERRUPT
DATA TECHNICAL |
SERIES E M68HC11 |