an illegal opcode is detected and the interrupt is recognized, the current value of the program counter is stacked. After interrupt service is complete, reinitialize the stack pointer so repeated execution of illegal opcodes does not cause stack underflow. Left uninitialized, the illegal opcode vector can point to a memory location that contains an illegal opcode. This condition causes an infinite loop that causes stack underflow. The stack grows until the system crashes.
The illegal opcode trap mechanism works for all unimplemented opcodes on all four opcode map pages. The address stacked as the return address for the illegal opcode interrupt is the address of the first byte of the illegal opcode. Otherwise, it would be almost impossible to determine whether the illegal opcode had been one or two bytes. The stacked return address can be used as a pointer to the illegal opcode so the illegal opcode service routine can evaluate the offending opcode.
5.4.4 Software Interrupt
SWI is an instruction, and thus cannot be interrupted until complete. SWI is not inhibited by the global mask bits in the CCR. Because execution of SWI sets the I mask bit,
once an SWI interrupt begins, other interrupts are inhibited until SWI is complete, or 5 until user software clears the I bit in the CCR.
5.4.5 Maskable Interrupts
The maskable interrupt structure of the MCU can be extended to include additional external interrupt sources through the IRQ pin. The default configuration of this pin is a low-level sensitive wired-OR network. When an event triggers an interrupt, a software accessible interrupt flag is set. When enabled, this flag causes a constant request for interrupt service. After the flag is cleared, the service request is released.
5.4.6 Reset and Interrupt Processing
Figure 5-1 and Figure 5-2 illustrate the reset and interrupt process. Figure 5-1 illustrates how the CPU begins from a reset and how interrupt detection relates to normal opcode fetches. Figure 5-2 is an expansion of a block in Figure 5-1 and illustrates interrupt priorities. Figure 5-3 shows the resolution of interrupt sources within the SCI subsystem.
M68HC11 E SERIES |
RESETS AND INTERRUPTS |
MOTOROLA |
TECHNICAL DATA |
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5-11 |
HIGHEST
PRIORITY
POWER-ON RESET (POR)
DELAY 4064 E CYCLES
EXTERNAL RESET
CLOCK MONITOR FAIL
(WITH CME = 1)
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LOWEST |
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PRIORITY |
5 |
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COP WATCHDOG |
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TIMEOUT |
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(WITH NOCOP = 0) |
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LOAD PROGRAM COUNTER |
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LOAD PROGRAM COUNTER |
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LOAD PROGRAM COUNTER |
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WITH CONTENTS OF |
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WITH CONTENTS OF |
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WITH CONTENTS OF |
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$FFFE, $FFFF |
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$FFFC, $FFFD |
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$FFFA, $FFFB |
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(VECTOR FETCH) |
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(VECTOR FETCH) |
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(VECTOR FETCH) |
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SET BITS S, I, AND X |
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RESET MCU |
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HARDWARE |
1A |
BEGIN INSTRUCTION |
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SEQUENCE |
Y |
BIT X IN |
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CCR = 1? |
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N |
XIRQ |
Y |
STACK CPU |
PIN LOW? |
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REGISTERS |
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N |
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SET BITS I AND X |
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FETCH VECTOR |
2A |
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$FFF4, $FFF5 |
FLOW OUT OF RESET P1
Figure 5-1 Processing Flow out of Reset (1 of 2)
MOTOROLA |
RESETS AND INTERRUPTS |
M68HC11 E SERIES |
5-12 |
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TECHNICAL DATA |
STACK CPU
REGISTERS
SET BIT I IN CCR
FETCH VECTOR $FFF8, $FFF9
STACK CPU
REGISTERS
SET BIT I IN CCR
FETCH VECTOR $FFF6, $FFF7
RESTORE CPU
REGISTERS
FROM STACK
2A
Y |
BIT I IN |
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CCR = 1? |
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N |
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ANY I-BIT |
Y |
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INTERRUPT |
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PENDING? |
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N
FETCH OPCODE
Y ILLEGAL
OPCODE?
N
WAI Y INSTRUCTION?
N
Y SWI INSTRUCTION?
N
Y RTI INSTRUCTION?
N
EXECUTE THIS
INSTRUCTION
1A
STACK CPU
REGISTERS
5
STACK CPU
REGISTERS
N ANY
INTERRUPT
PENDING?
Y
SET BIT I IN CCR
RESOLVE INTERRUPT
PRIORITY AND FETCH
VECTOR FOR HIGHEST
PENDING SOURCE
SEE FIGURE 5–2
FLOW OUT OF RESET P2
Figure 5-1 Processing Flow out of Reset (2 of 2)
M68HC11 E SERIES |
RESETS AND INTERRUPTS |
MOTOROLA |
TECHNICAL DATA |
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5-13 |
BEGIN |
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X BIT |
YES |
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IN CCR |
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SET ? |
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NO |
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HIGHEST
YES
PRIORITY
INTERRUPT
?
NO
YES
IRQ ?
NO
5
YES
RTII = 1 ?
NO
YES
IC1I = 1 ?
NO
YES
IC2I = 1 ?
NO
YES
IC3I = 1 ?
NO
YES
OC1I = 1 ?
NO
2A
YES
XIRQ PIN 
SET X BIT IN CCR
LOW ?
FETCH VECTOR
$FFF4, FFF5
NO
FETCH VECTOR
FETCH VECTOR $FFF2, FFF3
REAL-TIME |
YES |
FETCH VECTOR |
INTERRUPT |
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$FFF0, FFF1 |
? |
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NO |
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TIMER |
YES |
FETCH VECTOR |
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$FFEE, FFEF |
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IC1F ? |
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NO |
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TIMER |
YES |
FETCH VECTOR |
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$FFEC, FFED |
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IC2F ? |
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NO |
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TIMER |
YES |
FETCH VECTOR |
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$FFEA, FFEB |
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IC3F ? |
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NO |
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TIMER |
YES |
FETCH VECTOR |
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$FFE8, FFE9 |
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OC1F ? |
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NO |
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2B
INT PRIORITY RES P1
Figure 5-2 Interrupt Priority Resolution (1 of 2)
MOTOROLA |
RESETS AND INTERRUPTS |
M68HC11 E SERIES |
5-14 |
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TECHNICAL DATA |