- •1 Debug system overview
- •Figure 1. Debug system block diagram
- •2 Communication layer
- •Figure 2. SWIM pin external connections
- •3 Single wire interface module (SWIM)
- •3.1 Operating modes
- •Figure 3. SWIM activation sequence
- •Figure 5. SWIM entry sequence
- •3.2 SWIM entry sequence
- •Figure 4. SWIM activation timing diagram
- •3.3 Bit format
- •3.3.1 High speed bit format
- •Figure 6. High speed bit format
- •3.3.2 Low speed bit format
- •Figure 7. Low speed bit format
- •3.4 SWIM communication protocol
- •Figure 8. Command format (Host -> Target)
- •Figure 9. Data format (Target -> Host)
- •3.5 SWIM commands
- •3.5.1 SRST: system reset
- •3.5.2 ROTF: read on the fly
- •3.5.3 WOTF: write on the fly
- •3.6 SWIM communication reset
- •3.7 CPU register access
- •3.8 SWIM communication in Halt mode
- •3.9 Physical layer
- •Figure 10. Timings on SWIM pin
- •3.10 STM8 SWIM registers
- •3.10.1 SWIM control status register (SWIM_CSR)
- •3.10.2 SWIM clock control register (CLK_SWIMCCR)
- •4 Debug module (DM)
- •4.1 Introduction
- •4.2 Main features
- •Figure 11. Debug module block diagram
- •4.3 Debug
- •4.3.1 Reset
- •4.3.2 Breakpoints
- •4.3.3 Abort
- •4.3.4 Watchdog control
- •4.3.5 Interaction with SWIM
- •4.4 Breakpoint decoding table
- •4.5 Software breakpoint mode
- •4.6 Timing description
- •Figure 12. STM8 Instruction Model
- •4.7 Abort
- •Figure 13. STM8 Debug Module Stall Timing
- •4.8 Data breakpoint
- •Figure 14. STM8 DM Data Break Timing
- •4.9 Instruction breakpoint
- •Figure 15. STM8 DM instruction break timing
- •4.10 Step mode
- •Figure 16. STM8 DM step timing
- •4.11 Application notes
- •4.11.1 Illegal Memory access
- •4.11.2 Forbidden stack access
- •4.11.3 DM break
- •4.12 DM registers
- •4.12.1 DM breakpoint register 1 extended byte (DM_BKR1E)
- •4.12.2 DM breakpoint register 1 high byte (DM_BKR1H)
- •4.12.3 DM breakpoint register 1 low byte (DM_BKR1L)
- •4.12.4 DM breakpoint register 2 extended byte (DM_BKR2E)
- •4.12.5 DM breakpoint register 2 high byte (DM_BKR2H)
- •4.12.6 DM breakpoint register 2 low byte (DM_BKR2L)
- •4.12.7 DM control register 1 (DM_CR1)
- •4.12.8 DM control register 2 (DM_CR2)
- •4.12.9 DM control/status register 1 (DM_CSR1)
- •4.12.10 DM control/status register 2 (DM_CSR2)
- •4.12.11 DM enable function register (DM_ENFCTR)
- •4.12.12 Summary of SWIM, DM and core register maps
- •Appendix A Description of the DM_ENFCTR register for each STM8 product
- •Table 6. Peripherals which are frozen by the bits of the DM_ENFCTR register for each STM8 product
- •Revision history
UM0470 |
Description of the DM_ENFCTR register for each STM8 product |
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Appendix A Description of the DM_ENFCTR register for each STM8 product
Some peripherals can be frozen through the debug module during debug using the DM_ENFCTR register (address: 7F9Ah). Table 6 shows the peripherals which are frozen by the bits (ENFCT0 to ENFCT7) of the DM_ENFCTR register.
Table 6. Peripherals which are frozen by the bits of the DM_ENFCTR register for each STM8 product
DM_ENFCTR |
STM8AF51A |
STM8AF616 |
STM8AF51B |
STM8S103/903 |
STM8L101 |
STM8L15x |
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STM8S207/208 |
STM8S105 |
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register |
(128 Kbyte die) |
(32 Kbyte die) |
(256 Kbyte die) |
(8 Kbyte die) |
(8 Kbyte die) |
(32 Kbyte die) |
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Bit |
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Peripheral |
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ENFCT0 |
Timer4/ |
Timer4/ |
Timer4/ |
Timer4/ |
I2C |
I2C |
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System timer |
System timer |
System timer |
System timer |
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ENFCT1 |
Timer2 |
Timer2 |
Tmer2 |
Tmer2 |
Timer2 |
Timer2 |
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ENFCT2 |
Timer3 |
Timer3 |
Tmer3 |
Not used |
Timer3 |
Timer3 |
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ENFCT3 |
Timer1 |
Timer1 |
Tmer1 |
Timer1 |
— |
Timer1 |
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bit not used |
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ENFCT4 |
— |
— |
— |
— |
Timer4 |
Timer4 |
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bit not used |
bit not used |
bit not used |
bit not used |
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ENFCT5 |
— |
— |
Tmer5 |
— |
— |
DMA |
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bit not used |
bit not used |
bit not used |
bit not used |
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ENFCT6 |
— |
— |
I2C2 |
— |
— |
RTC |
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bit not used |
bit not used |
bit not used |
bit not used |
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ENFCT7 |
I2C |
I2C |
I2C |
I2C |
— |
— |
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bit not used |
bit not used |
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Doc ID 14024 Rev 3 |
35/37 |
