- •1 Debug system overview
- •Figure 1. Debug system block diagram
- •2 Communication layer
- •Figure 2. SWIM pin external connections
- •3 Single wire interface module (SWIM)
- •3.1 Operating modes
- •Figure 3. SWIM activation sequence
- •3.2 SWIM entry sequence
- •Figure 4. SWIM activation timing diagram
- •Figure 5. SWIM entry sequence
- •3.3 Bit format
- •3.3.1 High speed bit format
- •Figure 6. High speed bit format
- •3.3.2 Low speed bit format
- •Figure 7. Low speed bit format
- •3.4 SWIM communication protocol
- •Figure 8. Command format (Host -> Target)
- •Figure 9. Data format (Target -> Host)
- •3.5 SWIM commands
- •3.5.1 SRST: system reset
- •3.5.2 ROTF: read on the fly
- •3.5.3 WOTF: write on the fly
- •3.6 SWIM communication reset
- •3.7 CPU register access
- •3.8 SWIM communication in Halt mode
- •3.9 Physical layer
- •Figure 10. Timings on SWIM pin
- •3.10 STM8 SWIM registers
- •3.10.1 SWIM control status register (SWIM_CSR)
- •3.10.2 SWIM clock control register (CLK_SWIMCCR)
- •4 Debug module (DM)
- •4.1 Introduction
- •4.2 Main features
- •Figure 11. Debug module block diagram
- •4.3 Debug
- •4.3.1 Reset
- •4.3.2 Breakpoints
- •4.3.3 Abort
- •4.3.4 Watchdog control
- •4.3.5 Interaction with SWIM
- •4.4 Breakpoint decoding table
- •4.5 Software breakpoint mode
- •4.6 Timing description
- •Figure 12. STM8 Instruction Model
- •4.7 Abort
- •Figure 13. STM8 Debug Module Stall Timing
- •4.8 Data breakpoint
- •Figure 14. STM8 DM Data Break Timing
- •4.9 Instruction breakpoint
- •Figure 15. STM8 DM instruction break timing
- •4.10 Step mode
- •Figure 16. STM8 DM step timing
- •4.11 Application notes
- •4.11.1 Illegal Memory access
- •4.11.2 Forbidden stack access
- •4.11.3 DM break
- •4.12 DM registers
- •4.12.1 DM breakpoint register 1 extended byte (DM_BKR1E)
- •4.12.2 DM breakpoint register 1 high byte (DM_BKR1H)
- •4.12.3 DM breakpoint register 1 low byte (DM_BKR1L)
- •4.12.4 DM breakpoint register 2 extended byte (DM_BKR2E)
- •4.12.5 DM breakpoint register 2 high byte (DM_BKR2H)
- •4.12.6 DM breakpoint register 2 low byte (DM_BKR2L)
- •4.12.7 DM control register 1 (DM_CR1)
- •4.12.8 DM control register 2 (DM_CR2)
- •4.12.9 DM control/status register 1 (DM_CSR1)
- •4.12.10 DM control/status register 2 (DM_CSR2)
- •4.12.11 DM enable function register (DM_ENFCTR)
- •4.12.12 Summary of SWIM, DM and core register maps
- •Appendix A Description of the DM_ENFCTR register for each STM8 product
- •Table 6. Peripherals which are frozen by the bits of the DM_ENFCTR register for each STM8 product
- •Revision history
UM0470 |
Communication layer |
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2 Communication layer
The SWIM is a single wire interface based on asynchronous, high sink (8 mA), open-drain, bidirectional communication.
While the CPU is running, the SWIM allows non-intrusive read/write accesses to be performed on-the-fly to the RAM and peripheral registers, for debug purposes.
In addition, while the CPU is stalled, the SWIM allows read/write accesses to be performed to any other part of the MCU’s memory space (Data EEPROM and program memory).
CPU registers (A, X, Y, CC, SP) can also be accessed. These registers are mapped in memory and can be accessed in the same way as other memory addresses.
●Register, peripherals and memory can be accessed only when the SWIM_DM bit is set.
●When the system is in HALT, WFI or readout protection mode, the NO_ACCESS flag in the SWIM_CSR register is set. In this case, it is forbidden to perform any accesses because parts of the device may not be clocked and a read access could return garbage or a write access might not succeed.
The SWIM can perform a MCU device software reset.
The SWIM pin can also be used by the MCU target application as a standard I/O port with some restrictions if you also want to use it for debug. The safest way is to provide a strap option on the application PCB.
Figure 2. SWIM pin external connections
STM8
Application I/O
SWIM pin
SWIM interface for tools 

Jumper selection for debug purposes
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