4.3Debug

The DM registers can be read and written only through the SWIM interface. STM8 core has no access to these registers.

4.3.1Reset

Once the SWIM is active and SWIM_DM bit is set in SWIM_CSR register, a ‘data read’ breakpoint at the reset vector address is automatically set, due to the reset values of the debug module registers. This breakpoint can be used to initialize the debug session.

4.3.2Breakpoints

The DM generates a stall to the core when a breakpoint is reached. When the processor is stalled, the host can read or modify any address in memory. Access to the processor registers is explained in Section 3.7: CPU register access.

To restart the program execution, the STALL bit in DM_CSR2 must be cleared using the WOTF command of the SWIM protocol.

4.3.3Abort

To use the Abort function, the host must write the STALL bit in the DM_CSR2 using the SWIM WOTF command.

No interrupt is generated. The core is stalled in the current state. Using the SWIM commands, the host can read and modify the status of the MCU. If the CPU registers must be modified, the procedure described in Section 3.7: CPU register access has to be used.

The host can restart the program execution by resetting the STALL bit using the SWIM commands.

4.3.4Watchdog control

Using the WDGOFF bit in the DM control register 1 (DM_CR1) you can configure the Window Watchdog and Independent Watchdog counters to be stopped while the CPU is stalled by the Debug Module. This bit must be set before the watchdogs are activated. If a watchdog is enabled by Hardware Watchdog option bit, the WDGOFF bit has no effect on it.

4.3.5Interaction with SWIM

The SWIM sends the status bit which indicates the SWIM is active or not. When SWIM is not active, the DM will not generate any break/stall request to the CPU.