TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

For detailed information on the C55x DSP peripherals, see the following documents:

∙TMS320VC5501/5502 DSP Instruction Cache Reference Guide (literature number SPRU630)

∙TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618)

∙TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module Reference Guide

(literature number SPRU146)

∙TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)

∙TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature number SPRU613)

∙TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592)

∙TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide (literature number SPRU621)

∙TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) Reference Guide

(literature number SPRU597)

3.3Configurable External Ports and Signals

A number of pins on the 5502 have two functions, a feature that allows system designers to choose an appropriate media interface for his/her application without the need for a large pin-count package. Three muxes are included in the 5502 to control the configuration of these dual-function pins: the Parallel Port Mux, the Host Port Mux, and the Serial Port 2 Mux. The state of these muxes is set at reset based on the state of the GPIO6 and GPIO7 pins. The External Bus Selection Register (XBSR) reflects the configuration of these muxes after the 5502 comes out of reset.

3.3.1Parallel Port Mux

The Parallel Port Mux of the 5502 controls the function of 20 address signals (pins A[21:2]), 32 data signals (pins D[31:0]), and 16 control signals (pins C0 through C15). The Parallel Port Mux supports two different modes:

∙Full EMIF mode: The EMIF is enabled and its 20 address, 32 data, and 16 control signals are routed to their corresponding pins on the Parallel Port Mux.

∙Non-multiplexed HPI mode: The HPI is enabled with its 16 address, 16 data, and 9 control signals routed to their corresponding pins on the Parallel Port Mux. Moreover, 16 control signals, 4 address signals, and 16 data signals of the Parallel Port Mux that are not needed for HPI operation are set to general-purpose I/O (PGPIO).

The mode of the Parallel Port Mux is determined by the state of the GPIO6 pin at reset. If GPIO6 is low, the EMIF will be disabled and the HPI will be enabled in non-multiplexed mode: pins A[17:2] are set to HPI.HA[15:0] and pins D[15:0] are set to HPI.HD[15:0]. All address, data, and control signals in the Parallel Port Mux not needed by the HPI are set to parallel general-purpose I/O. The Parallel/Host Port Mux Mode bit field in the External Bus Selection Register (XBSR) will also be set to 0 to reflect the non-multiplexed HPI mode of the Parallel Port Mux.

If GPIO6 is high at reset, the HPI will be enabled in multiplexed mode and the EMIF will be fully enabled: pins A[21:2] are set to EMIF.A[21:2], pins D[31:0] are set to EMIF[31:0], and pins C[15:0] are set to their corresponding EMIF operation. The Parallel/Host Port Mux Mode bit field in the XBSR will be set to 1 to reflect the full EMIF mode of the Parallel Port Mux. Note that in multiplexed mode, the HPI will use the HD[7:0] pins to strobe in address and data information (see Section 3.8, Host-Port Interface (HPI), for more information on the operation of the HPI in multiplexed and non-multiplexed modes).

Table 3-4 lists the individual routing of the EMIF, PGPIO, and HPI signals to the external parallel address, data, and control buses.

3.3.2Host Port Mux

The 5502 Host Port Mux controls the function of 8 data signals (pins HD[7:0]) and 2 control signals (pins HC0 and HC1). The Host Port Mux supports two different modes:

∙8-bit multiplexed mode: The HPI's8 data and 2 control signals are routed to their corresponding pins on the Host Port Mux.

∙Parallel general-purpose I/O mode: All pins on the Host Port Mux are routed to PGPIO. The HPI is enabled to 16-bit (non-multiplexed) mode, but communicates through the Parallel Port Mux.

The mode of the Host Port Mux is determined by the state of the GPIO6 pin at reset. If GPIO6 is low, the pins of the Host Port Mux will be set to PGPIO. The HPI will still be enabled, but it will communicate through the Parallel Port Mux. The Parallel/Host Port Mux Mode bit of the External Bus Control Register will be set to 0 to reflect the PGPIO mode of the Host Port Mux.

If GPIO6 is high, the HPI will be enabled in 8-bit (multiplexed) mode: pins HD[7:0] are set to HPI.HD[7:0], and HC0 and HC1 are set to HPI.HAS and HPI.HBIL, respectively. The Parallel/Host Port Mux Mode bit field in the XBSR will be set to 1 to reflect the HPI multiplexed mode of the Host Port Mux. See Section 3.8, Host-Port Interface (HPI), for more information on the operation of the HPI in multiplexed and non-multiplexed modes.

Table 3-5 lists the individual routing of the HPI and PGPIO signals to the Host Port Mux pins.

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

Table 3-5. TMS320VC5502 Routing of Host Port Mux Signals

3.3.3Serial Port 2 Mux

The 5502 has three serial ports: McBSP0, McBSP1, and McBSP2, each of which has six signals. The signals for McBSP0 and McBSP1 are directly routed to pins on the 5502. Four of the pins for McBSP2 are multiplexed with two pins of the on-chip UART and two pins of the GPIO, the mode of the Serial Port 2 Mux determines which signals are routed to the 5502 pins.

The mode of the Serial Port 2 Mux is determined by the state of the GPIO7 pin at reset. If GPIO7 is low, the UART is enabled and its RX and TX pins are routed to the SP1 and SP3 pins, respectively. The GPIO3 and GPIO5 pins are routed to the SP0 and SP2 pins, respectively. In this mode, McBSP2 will be disabled and any writes or reads to/from its registers will result in a bus error if the PERITOEN bit of the Time-Out Control Register is set to 1.

If GPIO7 is high, McBSP2 will be enabled and its CLKX2, CLKR2, FSX2, and FSR2 signals will be routed to the SP0, SP1, SP2, and SP3 pins, respectively. In this mode, the UART will be disabled and any writes or reads to/from its registers will result in a bus error if the PERITOEN bit of the Time-Out Control Register is set to 1. GPIO3 and GPIO5 will not be available during this mode of the Serial Port 2 Mux.

Table 3-6 lists the individual routing of the McBSP2, UART, and GPIO signals to the Serial Port 2 Mux pins.

Table 3-6. TMS320VC5502 Routing of Serial Port 2 Mux Signals

TMS320VC5502

Fixed-Point Digital Signal Processor

www.ti.com

SPRS166J –APRIL 2001 –REVISED AUGUST 2006

Table 3-7. External Bus Selection Register Bit Field Description

The Parallel Port Mux is configured to support the HPI in 16-bit (non-multiplexed) mode and PGPIO. In this mode, the HPI is enabled and its 16 address, 16 data, and 9 control signals are routed to their corresponding pins on the Parallel Port Mux. The rest of the pins are routed to PGPIO. The EMIF cannot be used in this mode.

The Host Port Mux is configured to support PGPIO. In this mode, the Host Port Mux pins will be routed to PGPIO.

∙ Parallel/Host Port Mux Mode = 1:

The Parallel Port Mux is configured to support the 32-bit EMIF. In this mode, the EMIF is enabled and its 20 address, 32 data, and 16 control signals are routed to their corresponding pins on the Parallel Port Mux.

The Host Port Mux is configured to support the HPI in 8-bit (multiplexed) mode. In this mode, the HPI is enabled and its eight data/address and two control signals are routed to their corresponding pins on the Host Port Mux.